Patents by Inventor Hao-Hsuan Chang

Hao-Hsuan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200411384
    Abstract: A method for forming a semiconductor device is provided. A dielectric layer is formed on a substrate. First and second gate trenches are formed in the dielectric layer. First and second spacers are disposed in the first and the second gate trenches, respectively. A patterned photoresist is formed on the dielectric layer. The patterned photoresist masks the first region and exposes the second region. Multiple cycles of spacer trimming process are performed to trim a sidewall profile of the second spacer. Each cycle comprises a step of oxygen stripping and a successive step of chemical oxide removal. The patterned photoresist is then removed to reveal the first region.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Yao-Hsien Chung, Hao-Hsuan Chang, Ting-An Chien, Bin-Siang Tsai
  • Publication number: 20200350199
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.
    Type: Application
    Filed: June 4, 2019
    Publication date: November 5, 2020
    Inventors: Hao-Hsuan Chang, Hung-Chun Lee, Shu-Ming Yeh, Ting-An Chien, Bin-Siang Tsai
  • Publication number: 20200343371
    Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Inventors: Hao-Hsuan Chang, Bin-Siang Tsai, Ting-An Chien, Yi-Liang Ye
  • Patent number: 10622481
    Abstract: A method of rounding corners of a fin includes providing a substrate with a fin protruding from the substrate, wherein a pad oxide and a pad nitride entirely cover a top surface of the fin. Later, part of the pad oxide is removed laterally to expose part of the top surface of the fin. A silicon oxide layer is formed to contact two sidewalls of the fin and the exposed top surface, wherein two sidewalls and the top surface define two corners of the fin. After forming the silicon oxide layer, an annealing process is performed to round two corners of the fin. Finally, after the annealing process, an STI filling material is formed to cover the pad nitride, the pad oxide and the fin.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: April 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Hao-Hsuan Chang, Chia-Wei Hsu
  • Publication number: 20200052123
    Abstract: A method of rounding corners of a fin includes providing a substrate with a fin protruding from the substrate, wherein a pad oxide and a pad nitride entirely cover a top surface of the fin. Later, part of the pad oxide is removed laterally to expose part of the top surface of the fin. A silicon oxide layer is formed to contact two sidewalls of the fin and the exposed top surface, wherein two sidewalls and the top surface define two corners of the fin. After forming the silicon oxide layer, an annealing process is performed to round two corners of the fin. Finally, after the annealing process, an STI filling material is formed to cover the pad nitride, the pad oxide and the fin.
    Type: Application
    Filed: August 7, 2018
    Publication date: February 13, 2020
    Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Hao-Hsuan Chang, Chia-Wei Hsu
  • Publication number: 20190140074
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input/output (I/O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.
    Type: Application
    Filed: December 11, 2017
    Publication date: May 9, 2019
    Inventors: Hao-Hsuan Chang, Yao-Hsien Chung, Fu-Yu Tsai
  • Patent number: 10283618
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input/output (I/O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Hsuan Chang, Yao-Hsien Chung, Fu-Yu Tsai