Patents by Inventor Hao Liang

Hao Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961243
    Abstract: A geometric approach may be used to detect objects on a road surface. A set of points within a region of interest between a first frame and a second frame are captured and tracked to determine a difference in location between the set of points in two frames. The first frame may be aligned with the second frame and the first pixel values of the first frame may be compared with the second pixel values of the second frame to generate a disparity image including third pixels. One or more subsets of the third pixels that have a value above a first threshold may be combined, and the third pixels may be scored and associated with disparity values for each pixel of the one or more subsets of the third pixels. A bounding shape may be generated based on the scoring.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: April 16, 2024
    Assignee: NVIDIA Corporation
    Inventors: Dong Zhang, Sangmin Oh, Junghyun Kwon, Baris Evrim Demiroz, Tae Eun Choe, Minwoo Park, Chethan Ningaraju, Hao Tsui, Eric Viscito, Jagadeesh Sankaran, Yongqing Liang
  • Publication number: 20240120337
    Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: January 15, 2023
    Publication date: April 11, 2024
    Inventors: Ta-Chun LIN, Chih-Hung HSIEH, Chun-Sheng LIANG, Wen-Chiang HONG, Chun-Wing YEUNG, Kuo-Hua PAN, Chih-Hao CHANG, Jhon Jhy LIAW
  • Publication number: 20240120907
    Abstract: A system and a method for generating an arbitrary waveform of a microwave photon based on optical frequency tuning are provided. The system includes an optical frequency comb, a first optical distribution unit, a first photoelectric conversion unit, a frequency-shift drive circuit, and an optical frequency doubling/dividing unit, an optical frequency-shift combining optical circuit, a second photoelectric conversion unit, and a second electrical processing circuit. The optical frequency comb is used as the frequency source, with the features of high stability and low phase noise of the optical frequency comb, the arbitrary waveforms of microwave photons can be generated through optical frequency tuning control; the performance of the optical frequency comb is three orders of magnitude or more higher than that of the common microwave frequency sources, therefore, the waveforms with high-frequency, ultra-wideband, low phase noise, and high stability can be generated.
    Type: Application
    Filed: January 3, 2023
    Publication date: April 11, 2024
    Inventors: HAO ZHANG, YONGCHUAN XIAO, CAIBIN YU, XU LIANG, LIJUN SUN
  • Publication number: 20240121896
    Abstract: The present disclosure provides a circuit board including a first circuit layer, a dielectric layer on the first circuit layer, and a seed layer on the dielectric layer and directly contacting the first circuit layer, in which a top surface of the seed layer includes a levelled portion. The circuit board also includes a second circuit layer on the levelled portion of the seed layer, in which a grain boundary density of the second circuit layer is lower than that of a portion of the seed layer directly contacting the first circuit layer.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 11, 2024
    Inventors: Chien Jung CHEN, Jia Hao LIANG, Ching Ku LIN
  • Publication number: 20240113165
    Abstract: A semiconductor device includes a substrate, a first stack of semiconductor nanosheets, a second stack of semiconductor nanosheets, a gate structure and a first dielectric wall. The substrate includes a first fin and a second fin. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets is disposed on the second fin. The gate structure wraps the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall is disposed between the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall includes at least one neck portion between adjacent two semiconductor nanosheets of the first stack.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun LIN, Chun-Sheng Liang, Chih-Hao Chang, Jhon Jhy Liaw
  • Patent number: 11949056
    Abstract: The light emitting diode packaging structure includes a flexible substrate, a first adhesive layer, micro light emitting elements, a conductive pad, a redistribution layer, and an electrode pad. The first adhesive layer is disposed on the flexible substrate. The micro light emitting elements are disposed on the first adhesive layer and have a first surface facing to the first adhesive layer and an opposing second surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting element. The redistribution layer covers the micro light emitting elements and the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer. A thickness of the flexible substrate is less than 100 um.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: April 2, 2024
    Assignee: Lextar Electronics Corporation
    Inventors: Chih-Hao Lin, Jo-Hsiang Chen, Shih-Lun Lai, Min-Che Tsai, Jian-Chin Liang
  • Patent number: 11948983
    Abstract: A SiC ohmic contact preparation method is provided and includes: selecting a SiC substrate; preparing a graphene/SiC structure by forming a graphene on a Si-face of the SiC substrate; depositing an Au film on the graphene of the graphene/SiC structure; forming a first transfer electrode pattern on the Au film by a first photolithography; etching the Au film uncovered by the first transfer electrode pattern through a wet etching; etching the graphene uncovered by the Au film through a plasma etching after the wet etching; forming a second transfer electrode pattern on the SiC substrate by a second photolithography; depositing an Au material on the Au film exposed by the second transfer electrode pattern and forming an Au electrode and then annealing. The graphene reduces potential barrier associated with the SiC interface, specific contact resistance of ohmic contact reaches the order of 10?7˜10?8 ?·cm2, and the method has high repeatability.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: April 2, 2024
    Assignee: XIDIAN UNIVERSITY
    Inventors: Yanfei Hu, Hui Guo, Yuming Zhang, Jiabo Liang, Yanjing He, Hao Yuan, Yuting Ji
  • Publication number: 20240105805
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes channel structures vertically stacked over a substrate and a source/drain structure laterally attached to the channel structures in the first direction. The semiconductor structure also includes a dielectric wall structure laterally attached to the channel structures in the second direction. The second direction is different from the first direction. In addition, the dielectric wall structure includes a bottom portion and a cap layer formed over the bottom portion. The semiconductor structure also includes an isolation feature vertically overlapping the cap layer of the dielectric wall structure and a gate structure formed around the channel structures and covering a sidewall of the isolation feature.
    Type: Application
    Filed: February 2, 2023
    Publication date: March 28, 2024
    Inventors: Chun-Sheng LIANG, Hong-Chih CHEN, Ta-Chun LIN, Shih-Hsun CHANG, Chih-Hao CHANG
  • Patent number: 11942272
    Abstract: A method for preparing an aramid fiber electrochemical capacitor includes (1) immersing aramid fiber bundles in an aqueous solution; (2) adding polyvinylpyrrolidone into a silver ammonia solution to obtain a solution C, adding an aqueous glucose solution to the solution C to obtain aramid fiber bundles coated with silver nanoparticles; (3) adding the aramid fiber bundles into an aqueous solution containing ?-(2,3-glycidoxy) propyltrimethoxysilane; (4) adding the aramid fiber bundles coated by silver nanoparticles with epoxy groups into an ethanol containing carbon nanotubes with carboxyl groups; (5) adding the aramid fiber bundles with two-layered coatings into an aqueous solution containing pyrrole; (6) heating a mixture of a polyvinyl alcohol, an acid, and water to obtain a polyvinyl alcohol gel, immersing two strands of the aramid fiber bundles, carbon nanotubes and silver nanoparticle in the polyvinyl alcohol gel, and twisting the two strands together to obtain the aramid fiber electrochemical capacitor.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: March 26, 2024
    Assignee: SOOCHOW UNIVERSITY
    Inventors: Aijuan Gu, Hao Fang, Guozheng Liang, Li Yuan
  • Patent number: 11935804
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Publication number: 20240088149
    Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.
    Type: Application
    Filed: February 15, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Ming-Heng TSAI, Huang-Chao CHANG, Chun-Sheng LIANG, Chih-Hao CHANG, Jhon Jhy LIAW
  • Publication number: 20240088278
    Abstract: A semiconductor structure includes spaced apart first and second fins over a substrate, a separating wall over the substrate and having opposite first and second wall surfaces, multiple first channel features extending away from the first wall surface over the first fin such that the first channel features are spaced apart, multiple second channel features extending away from the second wall surface over the second fin such that the second channel features are spaced apart, two spaced apart first epitaxial structures on the first fin such that each first channel feature interconnects the first epitaxial structures, two spaced apart second epitaxial structures on the second fin such that each second channel feature interconnects the second epitaxial structures, and a dielectric structure including at least one bottom dielectric portion separating at least one of the first and second epitaxial structures from a corresponding first and second fins.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Chun-Sheng LIANG, Chun-Wing YEUNG, Chih-Hao CHANG
  • Publication number: 20240079447
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first stack structure formed over a substrate, and the first stack structure includes a plurality of nanostructures that extend along a first direction. The semiconductor structure includes a second stack structure formed adjacent to the first stack structure, and the second stack structure includes a plurality of nanostructures that extend along the first direction. The semiconductor structure includes a first gate structure formed over the first stack structure, and the first gate structure extends along a second direction. The semiconductor structure also includes a dielectric wall between the first stack structure and the second stack structure, and the dielectric wall includes a low-k dielectric material, and the dielectric wall is connected to the first stack structure and the second stack structure.
    Type: Application
    Filed: February 3, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun LIN, Chun-Sheng LIANG, Kuo-Hua PAN, Chih-Hao CHANG, Jhon-Jhy LIAW
  • Patent number: 11924961
    Abstract: A circuit board includes a conductive metal layer, at least one insulating layer, at least one thermally conductive insulating layer and a heat dissipation element. The conductive metal layer is mainly used to transmit electronic signals. The insulating layer is connected to the conductive metal layer. The thermally conductive insulating layer is sandwiched between the conductive metal layer and the insulating layer, and thermally contacts the conductive metal layer, and is used for thermally conducting the heat of the conductive metal layer. The heat dissipation element is in thermal contact with the thermally conductive insulating layer, and is used to conduct the heat of the thermally conductive insulating layer to the outside through a heat dissipation channel.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Ai Jing Lin, Chung-Yu Lan, Jia Hao Liang
  • Patent number: 11921090
    Abstract: A whole-vehicle-based method for evaluating extreme pressure and antiwear properties of grease includes injecting the grease onto a key bearing pin and causing the engineering machine to operate without load is disclosed. The method includes causing the engineering machine to operate under a load of 10% to 150% rated load at least once, viewing and analyzing a wear condition of a surface of the bearing pin, and issuing a whole-vehicle-based evaluation report of extreme pressure and antiwear properties of grease. The engineering machine is caused to operate once under a load of 10% to 150% rated load for 0.5 min to 100 h.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: March 5, 2024
    Assignee: Guangxi Liugong Machinery Co., Ltd.
    Inventors: Bo Lin, Li Zhang, Xiaona Wan, Jie Shao, Huiliang Xin, Hao Liang, Jinqiong Luo, Mingfeng Tan, Mingzhi Lin, Guoqing Hou
  • Publication number: 20240071538
    Abstract: The present disclosure provides a multi-state one-time programmable (MSOTP) memory circuit including a memory cell and a programming voltage driving circuit. The memory cell includes a MOS storage transistor, a first MOS access transistor and a second MOS access transistor electrically connected to store two bits of data. When the memory cell is in a writing state, the programming voltage driving circuit outputs a writing control potential to the gate of the MOS storage transistor, and when the memory cell is in a reading state, the programming voltage driving circuit outputs a reading control potential to the gate of the MOS storage transistor.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 29, 2024
    Inventors: CHEN-FENG CHANG, YU-CHEN LO, TSUNG-HAN LU, SHU-CHIEH CHANG, CHUN-HAO LIANG, DONG-YU WU, MENG-LIN WU
  • Publication number: 20240071888
    Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.
    Type: Application
    Filed: August 28, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chang Lin, Yen-Fu Su, Chin-Liang Chen, Wei-Yu Chen, Hsin-Yu Pan, Yu-Min Liang, Hao-Cheng Hou, Chi-Yang Yu
  • Patent number: 11916105
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bwo-Ning Chen, Xusheng Wu, Pin-Ju Liang, Chang-Miao Liu, Shih-Hao Lin
  • Patent number: 11916983
    Abstract: An online meeting system begins the process of connecting a user to an online meeting when a request is received from a user to start or join the online meeting. In response to the request, a pre-meeting user interface (UI) is displayed having a user interface control which, when activated, enables transmission of audio and/or video data for the online meeting, and prior to activation of the control, connection parameters are shared with an online meeting service to preheat the meeting. In response to activation of the control, transmission of audio and/or video data for the online meeting is enabled.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: February 27, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Nagaswapna Bhamidipati, Xin He, Milica Jovanovic, Artur Pawel Kania, Namendra Kumar, Rui Liang, Yue Li, Joel Harodi Marquez Catano, Abhilash Chandrasekharan Nair, Gaurav Pancholi, Jindrich Parus, Martin Petrla, Denis Postu, Rama Krishan Prasad Satya Prakash, Kensaku Sueda, Balvinder Kaur Thind, Hao Xu
  • Patent number: 11883859
    Abstract: A laser cleaning method and device for improving uniformity of a laser cleaning surface are provided. The laser cleaning method includes: applying a peaked-top sine wave signal to a motor; controlling a galvanometer to swing in a reciprocated manner by the motor; shaping a laser beam emitted by a laser to a linear beam by the reciprocated swing of the galvanometer; and performing laser cleaning using the shaped linear beam.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: January 30, 2024
    Assignee: INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES
    Inventors: Xuechun Lin, Zhiyan Zhang, Haijun Yu, Houwang Zhu, Quansheng Zeng, Zhiyong Dong, Hao Liang, Wenhao Ma, Hongyang Wang