Patents by Inventor Hao Lin

Hao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972363
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obtaining a plurality of model representations of predictive models, each model representation associated with a respective user and expresses a respective predictive model, and selecting a model implementation for each of the model representations based on one or more system usage properties associated with the user associated with the corresponding model representation.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 30, 2024
    Assignee: Google LLC
    Inventors: Wei-Hao Lin, Travis H. K. Green, Robert Kaplow, Gang Fu, Gideon S. Mann
  • Patent number: 11973010
    Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: April 30, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Hao-Lin Yen, Heng-Chi Huang, Yong-Zhong Hu
  • Patent number: 11973039
    Abstract: A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed next to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Hao Sung, Hsuan-Yu Chen, Yu-Kai Lin
  • Patent number: 11972557
    Abstract: Provided are a vibration object monitoring method and apparatus, a computer device, and a storage medium. The method includes: in response to detecting that a vibration object exists in a monitoring video picture for a target monitoring region, a vibration object region in the monitoring video picture is determined, where the vibration object region is a region where the vibration object is located in the monitoring video picture; displacement information of a key point of the vibration object in the vibration object region is recorded; vibration information of the vibration object in the monitoring video picture is determined based on the displacement information; and a vibration object monitoring result for the target monitoring region is generated according to the vibration information. The abnormal vibration monitoring can be performed on the vibration object in the target monitoring region in time according to this method.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: April 30, 2024
    Assignee: CSG POWER GENERATION CO., LTD.
    Inventors: Yumin Peng, Zhiqiang Wang, Hao Zhang, Hengjun Chen, Xun Hu, Tuixiang Feng, Liqun Sun, Man Chen, Yong Lu, Tao Liu, Kai Lin, Yulin Han
  • Publication number: 20240136366
    Abstract: A display panel and a display device are provided. The display panel includes a display region and a non-display region. The non-display region includes a demultiplexing circuit, a fanout wire, and a clock signal line. An input terminal of the demultiplexing circuit is electrically connected to the fanout wire, an output terminal of the demultiplexing circuit is electrically connected to a data line in the display region, and a control terminal of the demultiplexing circuit is electrically connected to the clock signal line. The display panel further includes an isolation signal line including an isolation portion, and an orthographic projection of the isolation portion on a plane where a substrate is located is between an orthographic projection of the clock signal line on the plane where the substrate is located and an orthographic projection of the fanout wire on the plane where the substrate is located.
    Type: Application
    Filed: January 4, 2024
    Publication date: April 25, 2024
    Applicant: Xiamen Tianma Microelectronics Co., Ltd.
    Inventors: Guangdeng YANG, Yiqiang LIN, Dongxu QIU, Hao WU, Poping SHEN
  • Publication number: 20240137483
    Abstract: An exemplary embodiment of the invention provides an image processing method for a virtual reality display system. The method includes: enabling a first shared buffer and a second shared buffer; performing an image capturing operation to obtain a first image from a virtual reality scene; storing the first image to the first shared buffer; in response to that the storing of the first image is finished, reading the first image from the first shared buffer; performing a depth estimation operation on the first image to obtain depth information corresponding to the first image; storing the depth information to the second shared buffer; in response to that the storing of the depth information is finished, reading the depth information from the second shared buffer; performing an image generation operation according to the depth information to generate a pair of second images corresponding to the virtual reality scene; and outputting the pair of second images by a display of the virtual reality display system.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Applicant: Acer Incorporated
    Inventors: Sergio Cantero Clares, Wen-Cheng Hsu, Shih-Hao Lin, Chih-Haw Tan
  • Publication number: 20240136428
    Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu
  • Publication number: 20240136298
    Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Publication number: 20240136291
    Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 25, 2024
    Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
  • Publication number: 20240136418
    Abstract: A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng CHEN, Chun-Hsiung LIN, Chih-Hao WANG
  • Patent number: 11964520
    Abstract: A packaging method for a tire pressure monitoring sensor includes a step of placing, a step of pouring, and a step of hardening. In the step of placing, a sensing transmission module is put into a cavity of a modeling unit, and a positioning portion in the cavity restricts the sensing transmission module from moving transversely and toward an inner bottom of the cavity. In the step of pouring, a rubber compound is poured into the cavity and fills the cavity. The sensing transmission module is coated by the rubber compound to form a case on the outer surface of the sensing transmission module. In the step of hardening, the case is hardened and integrally formed with the sensing transmission module to form a tire pressure monitoring sensor which is removed from the cavity.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: April 23, 2024
    Assignee: SYSGRATION LTD.
    Inventors: Sheng-Hao Lee, Shih-Yao Lin
  • Patent number: 11967594
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 11966544
    Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.
    Type: Grant
    Filed: May 25, 2023
    Date of Patent: April 23, 2024
    Assignee: Apple Inc.
    Inventors: Shinya Ono, Suhwan Moon, Dong-Gwang Ha, Jiaxi Hu, Hao-Lin Chiu, Kwang Soon Park, Hassan Edrees, Wen-I Hsieh, Jiun-Jye Chang, Chin-Wei Lin, Kyung Wook Kim
  • Patent number: 11964201
    Abstract: A modular pneumatic somatosensory device comprises a main body, a plurality of airbags, a plurality of inflating modules and a control module. The airbags are detachably disposed at different positions of the main body, and at least a part of the airbags have different sizes. The inflating modules are detachably disposed on the main body, and each inflating module is correspondingly connected with at least one of the airbags. The control module is detachably disposed on the main body and is electrically connected with the inflating modules. The control module controls the inflating modules to inflate the corresponding airbags according to a control signal.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: April 23, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Jen-Hui Chuang, June-Hao Hou, Chi-Li Cheng, Han-Ting Lin
  • Patent number: 11967591
    Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Ching-Yi Lin, Jyh Chwen Frank Lee
  • Publication number: 20240124310
    Abstract: A method for preparing a three-dimensional carbon nanotube composite structure comprises: providing a substrate; subjecting the substrate to nickel ion modification treatment to form at least one nickel ion nuclear seed on the substrate; providing a hydrogen gas to pass through the substrate and heating the substrate to a reduction temperature for reducing the nickel ion nuclear seed by the hydrogen gas at the reduction temperature; and supplying a carbon source gas and a protective gas to pass through the substrate and heating the substrate to a growth temperature so that the carbon atoms generated by the carbon source gas through the catalytic cracking of the nickel ion nuclear seed are deposited on the bottom of the nickel ion nuclear seed to form a carbon nanotube gradually, wherein the growth temperature is greater than or equal to the reduction temperature. The three-dimensional carbon nanotube composite structure prepared by the method and its application are also disclosed.
    Type: Application
    Filed: October 13, 2022
    Publication date: April 18, 2024
    Inventors: Hao-Lin HSU, Shuhn-Shyurng HOU
  • Publication number: 20240128216
    Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 18, 2024
    Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Ching-Chun Wang, Hsiao-Hui Tseng, Chen-Jong Wang, Dun-Nian Yaung
  • Publication number: 20240130066
    Abstract: A tray and an electronic device using the same are provided. The tray used to carry an expansion card includes a base, a tray body, a sliding plate, and a limiting spring. The tray body is slidably disposed on the base and has a base portion and two side walls disposed on two sides of the base portion. The sliding plate is slidably disposed on the base portion and is able to be moved away from or close to one of the side walls relative to the tray body selectively. The limiting spring is disposed on the base portion and is used to limit the sliding plate.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 18, 2024
    Applicant: Wistron Corporation
    Inventors: Yu-Chen Lin, Li-Shu Chen, Ching-Hao Chen
  • Publication number: 20240128422
    Abstract: A display module includes a substrate, a plurality of pixel units are arrayed on the substrate, and each of the pixel units is provided with at least three light-emitting chips, and the centers of at least three light-emitting chips are not collinear; and the projections of at least three light-emitting chips along a first direction at least partially overlap, and the projections of at least three light-emitting chips along a second direction at least partially overlap where the first direction is perpendicular to the second direction.
    Type: Application
    Filed: October 17, 2023
    Publication date: April 18, 2024
    Inventors: Yuanbin Lin, Hao Li, Bibo Li
  • Publication number: 20240128313
    Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 18, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Tse-Hsiao LIU, Chih-Wei LIN, Po-Hao CHIU, Pi-Kuang CHUANG, Ching-Yi HSU