Patents by Inventor Hao Luan
Hao Luan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9760432Abstract: An intelligent code apparatus, method, and computer program are provided for use with memory. In operation, a subset of data stored in a first memory is identified. Such subset of the data stored in the first memory is processed, to generate a code. The code is then stored in a second memory, for use in reconstructing at least a portion of the data.Type: GrantFiled: July 28, 2015Date of Patent: September 12, 2017Assignee: Futurewei Technologies, Inc.Inventors: Hao Luan, Alan Gatherer, Sriram Vishwanath, Casen Hunger, Hardik Jain
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Publication number: 20170153824Abstract: A method, system, and architecture for efficiently accessing data in a memory shared by multiple processor cores that reduces the probability of bank conflicts and decreases latency is provided. In an embodiment, a method for accessing data in a memory includes determining, by a scheduler, a read pattern for reading data from memory to serve requests in a plurality of bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least some of the data stored in the plurality of memory banks; reading a first data from a first memory bank; reading coded data from one of the coding banks; and determining the second data according to the coded data and the first data.Type: ApplicationFiled: December 1, 2015Publication date: June 1, 2017Inventors: Hao Luan, Alan Gatherer, Sriram Vishwanath, Casen Hunger, Hardik Jain
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Publication number: 20170103076Abstract: A computation system-on-a-chip (CSoC) includes a first scalable distributed real-time Data Warehousing (sdrDW) engine and a network interface coupled to the first sdrDW engine, where the network interface is coupled to an interconnect, and where the CSoC is configured to transmit a task request over the interconnect to a first networked bulk storage controller (NBSC) requesting that a task be performed on a bulk storage medium.Type: ApplicationFiled: September 13, 2016Publication date: April 13, 2017Inventors: Debashis Bhattacharya, Alan Gatherer, Alex Elisa Chandra, Mark Brown, Hao Luan, Ashish Rai Shrivastava
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Patent number: 9612651Abstract: Function resources/memory resources and an associated resource controller configured to assign a first portion of the function resources/memory resources to at least one processing element in response to an access request from the processing element. The resource controller changes a power mode of the first portion of the function resources/memory resources as a function of the first portion assignment, and leaves an unassigned portion of the function resources/memory resources in a power down mode in a self-governing nature. The resource controller enables the processing element to access the first portion of the function resources/memory resources in response to the access request received from the processing element. The function resources/memory resources, resource controllers and one or more processing elements may comprise a system on a chip (SoC).Type: GrantFiled: January 21, 2015Date of Patent: April 4, 2017Assignee: FUTUREWEI TECHNOLOGIES, INC.Inventors: Hao Luan, Alan Gatherer
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Publication number: 20170031619Abstract: A method includes receiving a first request, from a first master core, to access data in one of a plurality of memory banks. It is determined whether an access to the data is stalled by virtue of a second request, from a second master core, to access the data in the one of the plurality of memory banks, the second request currently being serviced. In response to a determination that the access to the requested data is stalled, the first request is serviced by accessing data in one of a plurality of coding banks, each coding bank smaller in size than each memory bank.Type: ApplicationFiled: July 28, 2015Publication date: February 2, 2017Inventors: Hao Luan, Alan Gatherer, Sriram Vishwanath, Casen Hunger, Hardik Jain
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Publication number: 20170031762Abstract: An intelligent code apparatus, method, and computer program are provided for use with memory. In operation, a subset of data stored in a first memory is identified. Such subset of the data stored in the first memory is processed, to generate a code. The code is then stored in a second memory, for use in reconstructing at least a portion of the data.Type: ApplicationFiled: July 28, 2015Publication date: February 2, 2017Inventors: Hao Luan, Alan Gatherer, Sriram Vishwanath, Casen Hunger, Hardik Jain
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Publication number: 20170031606Abstract: Systems and techniques for dynamic coding of memory regions are described. A described technique includes monitoring accesses to a group of memory regions, each region including two or more portions of a group of data banks; detecting a high-access memory region based on whether accesses to a region of the group of memory regions exceeds a threshold; generating coding values of a coding region corresponding to the high-access memory region, the high-access memory region including data values distributed across the group of banks; and storing the coding values of the coding region in a coding bank.Type: ApplicationFiled: July 28, 2015Publication date: February 2, 2017Inventors: Hao Luan, Alan Gatherer, Sriram Vishwanath, Casen Hunger, Hardik Jain
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Publication number: 20170017412Abstract: A controller for a shared memory is disclosed. The controller comprises a transaction scanner configured to scan-in a plurality of transactions to access the shared memory and to divide the transactions into beat-level memory access commands. The controller also comprises a command super-arbiter comprising a plurality of command arbiters corresponding to a plurality of shared memory blocks in the shared memory. The command super-arbiter is configured to access a quality of service for each of the transactions, arbitrate the beat-level memory access commands associated with the transactions based on the quality of service for each of the plurality of transactions, and dispatch the beat-level memory access commands to the shared memory blocks based on results of arbitrating the beat-level memory access commands.Type: ApplicationFiled: July 13, 2015Publication date: January 19, 2017Inventors: Hao Luan, Alan Gatherer, Bin Yang
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Patent number: 9335934Abstract: Disclosed herein are a shared memory controller and a method of controlling a shared memory. An embodiment method of controlling a shared memory includes concurrently scanning-in a plurality of read/write commands for respective transactions. Each of the plurality of read/write commands includes respective addresses and respective priorities. Additionally, each of the respective transactions is divisible into at least one beat and at least one of the respective transactions is divisible into multiple beats. The method also includes dividing the plurality of read/write commands into respective beat-level read/write commands and concurrently arbitrating the respective beat-level read/write commands according to the respective addresses and the respective priorities. Concurrently arbitrating yields respective sequences of beat-level read/write commands corresponding to the respective addresses.Type: GrantFiled: April 29, 2014Date of Patent: May 10, 2016Assignee: Futurewei Technologies, Inc.Inventors: Hao Luan, Alan Gatherer, Yan Bei, Jun Ying
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Publication number: 20160116971Abstract: Function resources/memory resources and an associated resource controller configured to assign a first portion of the function resources/memory resources to at least one processing element in response to an access request from the processing element. The resource controller changes a power mode of the first portion of the function resources/memory resources as a function of the first portion assignment, and leaves an unassigned portion of the function resources/memory resources in a power down mode in a self-governing nature. The resource controller enables the processing element to access the first portion of the function resources/memory resources in response to the access request received from the processing element. The function resources/memory resources, resource controllers and one or more processing elements may comprise a system on a chip (SoC).Type: ApplicationFiled: January 21, 2015Publication date: April 28, 2016Inventors: Hao Luan, Alan Gatherer
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Publication number: 20150309725Abstract: Disclosed herein are a shared memory controller and a method of controlling a shared memory. An embodiment method of controlling a shared memory includes concurrently scanning-in a plurality of read/write commands for respective transactions. Each of the plurality of read/write commands includes respective addresses and respective priorities. Additionally, each of the respective transactions is divisible into at least one beat and at least one of the respective transactions is divisible into multiple beats. The method also includes dividing the plurality of read/write commands into respective beat-level read/write commands and concurrently arbitrating the respective beat-level read/write commands according to the respective addresses and the respective priorities. Concurrently arbitrating yields respective sequences of beat-level read/write commands corresponding to the respective addresses.Type: ApplicationFiled: April 29, 2014Publication date: October 29, 2015Applicant: FUTUREWEI TECHNOLOGIES, INC.Inventors: Hao Luan, Alan Gatherer, Yan Bei, Jun Ying
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Publication number: 20140297178Abstract: The present disclosure relates to a navigation method, a device for navigation and a navigation system in the field of communication technique. Said method comprises steps of performing a location processing to obtain a location of the first terminal, acquiring a location of a second terminal; and navigating the second terminal based on navigation information from the location of the second terminal to a target location. The target location is a predetermined location or a current location of the first terminal. A first terminal for navigation comprises a location module, an acquiring module and a navigation module. A server for navigation comprises an acquiring module and a transmitting module. Said system comprises the first terminal and the server. The present disclosure accomplished a location-based navigation service and incorporated the location service and the navigation function so as to enhance the location service function and sufficiently meet with the user's requirements.Type: ApplicationFiled: June 17, 2014Publication date: October 2, 2014Inventors: Hao LUAN, Yingfeng ZHANG, Mu WANG
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Patent number: 8477658Abstract: An efficient media streaming method utilizing a globally load balanced overlay network. This method makes use of capacity per out-degree values to construct and maintain an overlay network for media streaming in a Peer-to-Peer environment.Type: GrantFiled: April 25, 2007Date of Patent: July 2, 2013Assignee: The Hong Kong University of Science and TechnologyInventors: Danny Hin Kwok Tsang, Hao Luan, Kin Wah Kwong
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Patent number: 7941774Abstract: Various apparatuses, methods and systems for creating an integrated circuit and performing a gate level simulation of a circuit are disclosed herein. For example, some embodiments of the present invention provide a system for performing a gate level simulation of a circuit including a computer system, a design verification tool and an output device. The design verification tool, executable on the computer system, includes a simulator and a partial timing model generator. The partial timing model generator is operable to generate a representation of the circuit for simulation by cutting a first portion of a circuit out of a full gate level netlist for the circuit and leaving a second portion of the circuit represented by the full gate level netlist, and to overlay a simplified representation of the first portion of the circuit over the representation of the circuit. The first portion of the circuit is cut out at timing paths.Type: GrantFiled: August 4, 2008Date of Patent: May 10, 2011Assignee: Texas Instruments IncorporatedInventors: Hao Luan, Steve P. Korson
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Publication number: 20100031209Abstract: Various apparatuses, methods and systems for creating an integrated circuit and performing a gate level simulation of a circuit are disclosed herein. For example, some embodiments of the present invention provide a system for performing a gate level simulation of a circuit including a computer system, a design verification tool and an output device. The design verification tool, executable on the computer system, includes a simulator and a partial timing model generator. The partial timing model generator is operable to generate a representation of the circuit for simulation by cutting a first portion of a circuit out of a full gate level netlist for the circuit and leaving a second portion of the circuit represented by the full gate level netlist, and to overlay a simplified representation of the first portion of the circuit over the representation of the circuit. The first portion of the circuit is cut out at timing paths.Type: ApplicationFiled: August 4, 2008Publication date: February 4, 2010Inventors: Hao Luan, Steve P. Korson
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Publication number: 20080077893Abstract: The present invention provides a method for verifying interconnected blocks in a top-block by creating one or more assertions for each input/output of one or more blocks to be used within the top-block, creating one or more assertions for each input/output of the top-block, providing a stimulus intended to cause each assertion to be triggered, and verifying that a result for each assertion was correct. The assertions verify that a valid functional mode caused a change in an output or a valid functional mode received the change in an input. A computer program embodied on a computer readable medium can implement the foregoing steps as one or more code segments.Type: ApplicationFiled: September 26, 2006Publication date: March 27, 2008Applicant: Texas Instruments IncorporatedInventors: Steven Korson, Hao Luan
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Publication number: 20070280255Abstract: An efficient media streaming method utilizing a globally load balanced overlay network. This method makes use of capacity per out-degree values to construct and maintain an overlay network for media streaming in a Peer-to-Peer environment.Type: ApplicationFiled: April 25, 2007Publication date: December 6, 2007Applicant: The Hong Kong University of Science and TechnologyInventors: Danny Tsang, Hao Luan, Kin-Wah Kwong