Abstract: In cancers such as prostate cancer, the combination of PTEN loss and activation of Myc activates an adaptive stress response that enables tumor cells to escape the stress of massively upregulated protein synthesis. This pro-survival response is mediated by the PERK-phosphorylated eIF2? axis of the UPR adaptive response. Agents that disrupt PERK-eIF2? pathways disrupt the adaptive response and lead to cancer cell death from uncontrolled growth. For example, ISRIB and derivatives may be employed as therapeutic agents to disrupt PERK-mediated adaptive mechanisms. Additionally PTEN loss and activation of Myc provides a diagnostic marker that enables better prognosis and the selection of amenable treatments.

Abstract: In cancers such as prostate cancer, the combination of PTEN loss and activation of Myc activates an adaptive stress response that enables tumor cells to escape the stress of massively upregulated protein synthesis. This pro-survival response is mediated by the PERK-phosphorylated eIF2? axis of the UPR adaptive response. Agents that disrupt PERK-eIF2? pathways disrupt the adaptive response and lead to cancer cell death from uncontrolled growth. For example, ISRIB and derivatives may be employed as therapeutic agents to disrupt PERK-mediated adaptive mechanisms. Additionally PTEN loss and activation of Myc provides a diagnostic marker that enables better prognosis and the selection of amenable treatments.

Abstract: A method and apparatus for collecting and evaluating biometric data of members of a group uses a mobile ad hoc network to relay information collected from each group member to a monitoring device. The information is collected from each group member using a chin strap biometric sensing device. The monitoring device is an endpoint of the mobile ad hoc network, and organizes the collected data for evaluation and display to a supervisor of the group. Any biometric parameter for a given group member that exceeds a preferred value can be flagged for immediate attention by the supervisor.

Abstract: A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. By allowing the sense amplifier to bias a memory cell being sensed to a selected one of multiple bias levels during a sensing operation, multiple target data states can be concurrently program verified, leading to higher performance when writing data.

Abstract: Apparatuses, systems, and methods are disclosed for current sensing for non-volatile memory. A current to voltage conversion circuit may convert a current coupled to a sense amplifier to an analog voltage at a sense node. A voltage to digital conversion circuit may convert an analog voltage at a sense node to a digital signal, based on a voltage difference between the sense node and a comparison node during a strobe time. A bias circuit may bias a comparison node to a bias voltage other than a reference voltage, at least during a strobe time.

Abstract: A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. To reduce noise, a decoupling capacitor is connected to the control gate of the discharge transistor and an auxiliary keeper current is run through the discharge transistor.

Abstract: A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. To reduce noise, a decoupling capacitor is connected to the control gate of the discharge transistor and an auxiliary keeper current is run through the discharge transistor.

Abstract: The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.

Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Abstract: A stereographic image associated with a panoramic camera can be identified. The panoramic camera can include of a set of lenses and an image sensor. A pixel degradation curve associated with the image and/or the hardware of the panoramic camera can be determined, as can a sensor geometry of an image sensor used by the panoramic camera. A fixed smoothing function based on the pixel degradation curve and/or the sensor geometry can be created. The fixed smoothing function can be applied to a stereographic image to modify the image so it includes substantially uniform image detail per image region.

Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Abstract: The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.

Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Abstract: In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs.

Abstract: In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.

Abstract: A wearable alert device includes an audio transducer and driver circuit that allows selection of either a high or low volume setting for driving the transducer. The driver circuit is operable in a single ended mode for low volume and a double ended mode for high volume. The single ended mode holds one terminal of the transducer low while the other is driven in correspondence with a clock signal, while the double ended mode drives one terminal in correspondence with the clock signal and the other terminal is inverted from the clock signal. The transducer is activated in response to an alert event, and can be driven according to a profile or pattern.

Abstract: A system of an alert puck, a mobile communication device, and an alert server for facilitating a VOIP session with the mobile communication device responsive to an emergency event triggered by the alert puck. The alert puck comprises a housing enclosing a sealed volume, a power supply and control circuitry that includes a personal area network (PAN) interface. The mobile communication device comprises an operating system, an alert application executing upon the operating system, and a wireless transceiver. The alert server contacts a set of one or more previously defined contact devices, conveys an emergency message, and facilitates the VOIP session with the alert application, when a button is pressed on the alert puck.

Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Abstract: Rather than supply an internal node of a non-volatile memory's sense amplifier from a supply level through a transistor by applying a voltage to the transistor's gate to clamp the node, the internal node is supplied by an op-amp through a pass gate. The op-amp receives feedback from above the pass gate. This allows a desired voltage level to be more quickly and accurately established on the node. Using a two-step reference level for the op-amp can further increases speed and accuracy. Biasing the op-amp with the external power supply can offer additional advantages.

Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.