Abstract: A circuit board includes a main board, a thermistor layer, a plurality of n-type semiconductor units and a plurality of p-type semiconductor units. The main board includes a first external structure, a second external structure, and an internal structure disposed between the first external structure and the second external structure. The internal structure includes a first internal circuit layer, a second internal circuit layer, and an insulating layer disposed between the first internal circuit layer and the second internal circuit layer. The thermistor layer is disposed on the insulating layer and the first internal circuit layer. The n-type semiconductor units and the p-type semiconductor units are electrically connected to the second internal circuit layer and the second external structure, in which the n-type semiconductor units and the p-type semiconductor units are alternately arranged in one direction.

Abstract: A method for manufacturing an integrated circuit device is provided. The method includes depositing an epitaxial stack comprising alternative first and second semiconductor layers over a semiconductor substrate; patterning the epitaxial stack to form first and second semiconductor fins; removing the first semiconductor layers in the first and second semiconductor fins, while leaving a first set of the second semiconductor layers in the first semiconductor fin and a second set of the second semiconductor layers in the second semiconductor fin; forming a gate dielectric layer around the first and second sets of the second semiconductor layers; depositing a gate metal layer over the gate dielectric layer; etching a recess in the gate metal layer and between the first and second sets of the second semiconductor layers, wherein the gate metal layer has a first portion below the recess; and forming a dielectric feature in the recess.

Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

Abstract: Gates having air gaps therein, and methods of fabrication thereof, are disclosed herein. An exemplary gate includes a gate electrode and a gate dielectric. A first air gap is between and/or separates a first sidewall of the gate electrode from the gate dielectric, and a second air gap is between and/or separates a second sidewall of the gate electrode from the gate dielectric. A dielectric cap may be disposed over the gate electrode, and the dielectric cap may wrap a top of the gate electrode. The dielectric cap may fill a top portion of the first air gap and a top portion of the second air gap. The gate may be disposed between a first epitaxial source/drain and a second epitaxial source/drain, and a width of the gate is about the same as a distance between the first epitaxial source/drain and the second epitaxial source/drain.

Abstract: A method may be applied to an electronic device configured with a foldable display. The display includes a first area, a second area, and a third area, and when the electronic device is in a folded form, an included angle between the first area and the third area is less than a first preset angle, and two sides of a third area are the first area and the second area. The method includes: displaying a first interface in the first area, where the first interface includes one or more touchable areas; determining a first touch area between a user and the third area; mapping a touch function of a first touchable area in the first interface to the first touch area; detecting a first operation in the first touch area; and controlling the first touchable area in the first interface based on the first operation.

Abstract: A semiconductor device may include one or more transistor structures that include a plurality of source/drain regions and a gate structure between the source/drain regions. The semiconductor device may further include one or more dielectric layers between a source/drain contact structure and a gate structure of the one or more of the transistor structures. The one or more dielectric layers may be manufactured using on oxidation treatment process to tune the dielectric constant of the one or more dielectric layers. The dielectric constant of the one or more dielectric layers may be tuned to reduce the parasitic capacitance between the source/drain contact structure and the gate structure (which are conductive structures). In particular, the dielectric constant of the one or more spacer dielectric may be tuned using the oxidation treatment process to lower the as-deposited dielectric constant of the one or more dielectric layers.

Abstract: The embodiments of the disclosure provide a dada shuffling method, apparatus and device, a computer-readable storage medium and product. The method comprises: acquiring a data shuffling request; acquiring a shuffling request parameter linked list associated with the at least one data to be shuffled based on the data shuffling request; performing a merging operation on shuffling request parameters in the shuffling request parameter linked list according to the data amount of the data segment corresponding to the shuffling request parameter and memory buffer information to obtain at least one target request parameter; and caching the data to be shuffled corresponding to the at least one target request parameter to a predetermined remote direct memory access network card; and distributing respectively data segments associated with at least one data to be shuffled cached in the remote direct memory access network card to a target server of the data segment.

Abstract: An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

Abstract: A device includes a substrate, a first stack of semiconductor nanostructures vertically overlying the substrate, and a gate structure surrounding the semiconductor nanostructures and abutting an upper side and first and second lateral sides of the first stack. A first epitaxial region laterally abuts a third lateral side of the first stack, and a second epitaxial region laterally abuts a fourth lateral side of the first stack. A first inactive fin laterally abuts the first epitaxial region, and a second inactive fin laterally abuts the second epitaxial region and is physically separated from the first inactive fin by the gate structure.

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions.

Abstract: A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate laterally offset from the first semiconductor channel. A first gate structure and a second gate structure are over and laterally surround the first and second semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure. A dielectric feature over the inactive fin includes multiple layers of dielectric material formed through alternating deposition and etching steps.

Abstract: A silicon photonic chip, a LiDAR, and a mobile device are disclosed. The silicon photonic chip includes a cladding, a transceiving waveguide module, a first photoelectric detection module, and a first polarization rotator. An emitting waveguide of the transceiving waveguide module extends along a first direction and is configured to transmit and emit a detection light, and the first receiving waveguide of the transceiving waveguide module is arranged at intervals along a second direction from the emitting waveguide and is configured to receive and transmit an echo light. The first photoelectric detection module is configured to receive a first local oscillator light and the echo light output by the first receiving waveguide. The first polarization rotator is disposed upstream of the first photoelectric detection module.

Abstract: The present disclosure describes a structure including a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate and a method of forming the structure. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.

Abstract: A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.

Abstract: A method for estimating performance values of chips includes: (A) using oscillation period vectors of a to-be-divide chip set to train a first neural network model to obtain a training error of the to-be-divided chip set, where in the first-time conducted step (A), the to-be-divided chip set includes the chips; (B) dividing the to-be-divided chip set into divided chip sets according to the training error; and (C) using oscillation period vectors of the divided chip sets as training data of a second neural network model, so that the second neural network model outputs weight vectors respectively corresponding to the divided chip sets. A product of oscillation period vector(s) of each divided chip set and a weight vector of the divided chip set is larger than a product of the oscillation period vector(s) of the divided chip set and a weight vector of each of rest of divided chip sets.