Patents by Inventor Hao Wang

Hao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250090577
    Abstract: A method for preparing a clay mineral biomaterial includes: mixing montmorillonite and a potassium permanganate solution to obtain a reaction solution; subjecting the reaction solution to a hydrothermal reaction; and washing and drying a product obtained after the hydrothermal reaction to obtain the clay mineral biomaterial. In the method, montmorillonite is used as a carrier, and nano-scale manganese dioxide particles are allowed to grow in situ on the montmorillonite carrier through a hydrothermal reaction. The nano-scale manganese dioxide particles are well dispersed and fixed on a surface of the montmorillonite carrier, which can prevent the nanoparticles from aggregating.
    Type: Application
    Filed: April 2, 2024
    Publication date: March 20, 2025
    Applicant: CHINA UNIVERSITY OF GEOSCIENCES (WUHAN)
    Inventors: Huaming YANG, Qianqian LIU, Hao WANG
  • Publication number: 20250098222
    Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.
    Type: Application
    Filed: November 26, 2024
    Publication date: March 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Xuan HUANG, Hou-Yu CHEN, Jin CAI, Zhi-Chang LIN, Chih-Hao WANG
  • Publication number: 20250098219
    Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.
    Type: Application
    Filed: February 15, 2024
    Publication date: March 20, 2025
    Inventors: Jung-Hung CHANG, Shih-Cheng CHEN, Tsung-Han CHUANG, Fu-Cheng CHANG, Wen-Ting LAN, Chia-Cheng TSAI, Kuo-Cheng CHIANG, Chih-Hao WANG, Wang-Chun Huang, Shi-Syuan Huang
  • Publication number: 20250097892
    Abstract: A method for sidelink positioning, a terminal device, and a network device are provided. The method includes: transmitting, by a first terminal device, a first sidelink positioning reference signal to a second terminal device by using a first sidelink resource, where the first sidelink resource is configured by a network device, or the first sidelink resource is selected by the first terminal device or the second terminal device from a sidelink resource pool.
    Type: Application
    Filed: December 2, 2024
    Publication date: March 20, 2025
    Applicant: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Hao WANG, Yi DING, Shichang ZHANG
  • Publication number: 20250098237
    Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a first transistor. The first transistor includes a first gate structure wrapping around a plurality of first nanostructures disposed over a substrate, a first source/drain feature electrically coupled to a topmost nanostructure of the plurality of first nanostructures and isolated from a bottommost nanostructure of the plurality of first nanostructures by a first dielectric layer, and a first semiconductor layer disposed between the substrate and the first source/drain feature, wherein the first source/drain feature is in direct contact with a top surface of the first semiconductor layer.
    Type: Application
    Filed: January 4, 2024
    Publication date: March 20, 2025
    Inventors: Jung-Hung Chang, Shih-Cheng Chen, Tsung-Han Chuang, Wen-Ting Lan, Chia-Cheng Tsai, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20250098293
    Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 20, 2025
    Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG, Kuan-Lun CHENG, Guan-Lin CHEN
  • Publication number: 20250098070
    Abstract: The first circuit board is a flexible printed circuit, and a stiffener and one or more first pads are disposed on a first surface of the first circuit board. The stiffener is provided with first through holes, at least one first pad is located in one first through hole of the the first through holes, and hardness of the stiffener is greater than hardness of the first circuit board. In addition, second pads are disposed on the second circuit board, and the at least one first pad is soldered to the second pad, to implement an electrical connection between the first circuit board and the second circuit board.
    Type: Application
    Filed: December 5, 2022
    Publication date: March 20, 2025
    Inventors: Tong ZHANG, Fan JIANG, Heyujia TANG, Haisheng ZHOU, Dan WEI, Kelin LI, Jiguang LI, Hao WANG
  • Publication number: 20250097904
    Abstract: Provided is a method for resource selection. The method is applicable to a terminal device, and includes selecting a transmission resource from a first resource set after resource exclusion on the first resource set; wherein any resource within the first resource set is a first resource, wherein the first resource corresponds to N consecutive time units in a time domain, N being an integer greater than 1.
    Type: Application
    Filed: November 20, 2024
    Publication date: March 20, 2025
    Inventors: Yi DING, Zhenshan ZHAO, Huei-Ming LIN, Hao WANG
  • Patent number: 12251722
    Abstract: A sprayer includes: a container; a passage including a transparent window, a first opening, a second opening and a resonator, wherein when liquid in the container is passed through the resonator via the first opening, the liquid is emitted as a gas via the second opening; and a removable detection unit disposed outside of the passage. The removable detection unit includes: a light source for illuminating the gas in the passage; an optical sensor disposed to detect a parameter of light reflected by the gas; and a processor coupled to the optical sensor for stopping the resonator from generating the gas when the parameter is below a threshold. The passage further includes a cavity disposed on a bottom surface of the passage in front of the optical sensor, wherein when the gas in the passage contacts the bottom surface, resultant water vapour will enter the cavity.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: March 18, 2025
    Assignee: PixArt Imaging Inc.
    Inventors: Chih-Hao Wang, Yang-Ming Chou, Chien-Yi Kao, Shih-Jen Lu, Chih-Ming Sun, Hsin-Yi Lin
  • Patent number: 12255103
    Abstract: A method includes receiving a substrate having a front side and a back side, forming a shallow trench in the substrate from the front side, forming a liner layer including a first dielectric material in the shallow trench, depositing a second dielectric material different from the first dielectric material on the liner layer to form an isolation feature in the shallow trench, forming an active region surrounded by the isolation feature, forming a gate stack on the active region, forming a source/drain (S/D) feature on the active region and on a side of the gate stack, thinning down the substrate from the back side such that the isolation feature is exposed, etching the active region to expose the S/D feature from the back side to form a backside trench, and forming a backside via feature landing on the S/D feature and surrounded by the liner layer.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Zhen Yu, Chia-Hao Chang, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 12255070
    Abstract: In a semiconductor structure, a first conductive feature is formed in a trench by PVD and a glue layer is then deposited on the first conductive feature in the trench before CVD deposition of a second conductive feature there-over. The first conductive feature acts as a protection layer to keep silicide from being damaged by later deposition of metal or a precursor by CVD. The glue layer extends along the extent of the sidewall to enhance the adhesion of the second conductive features to the surrounding dielectric layer.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Hsuan Lu, Kan-Ju Lin, Lin-Yu Huang, Sheng-Tsung Wang, Hung-Yi Huang, Chih-Wei Chang, Ming-Hsing Tsai, Chih-Hao Wang
  • Publication number: 20250084100
    Abstract: A method for preparing a nitrogen-containing polycyclic fused ring compound of formula I, and an intermediate thereof are provided. By this method, the compound of formula I can be produced on an industrial scale without column chromatography separation, purification steps such as silica gel column chromatography, or hydrogen. In addition, the preparation method effectively uses positional isomers IIIA and IIIB, and improves the yield of a target product from being adversely influenced by discarding positional isomer IIIA.
    Type: Application
    Filed: July 1, 2022
    Publication date: March 13, 2025
    Inventors: Jun ZHONG, Qin GAO, Minchun CHEN, Yongbo LIU, Hao WANG
  • Publication number: 20250087764
    Abstract: A configuration method for a plurality of serial codes of a battery management system, wherein the battery management system includes a master battery management device and a plurality of slave battery management devices. The configuration method comprises steps of: sending, by each slave battery management device, a notification message through a first communication interface, wherein each notification message includes an identification code of each slave battery management device; receiving, by the master battery management device, each notification message and acquiring each identification code from each notification message received; counting, by the master battery management device, a number of the identification codes and performing a configuration step when the number of the identification codes is determined to be equal to a predetermined number of connections. In the configuration step, the first to the last of the slave battery management devices are configured sequentially with a serial code.
    Type: Application
    Filed: September 9, 2024
    Publication date: March 13, 2025
    Applicant: MOBILETRON ELECTRONICS CO., LTD.
    Inventors: PIN-HAO WANG, WEN-CHUAN HUNG
  • Publication number: 20250087578
    Abstract: A semiconductor device and a method of manufacturing thereof are provided. The method comprises: forming a gate electrode over a substrate; forming source/drain regions beside the gate electrode; forming contact plugs on the source/drain regions; forming a dielectric layer over the contact plugs and the gate electrode; forming first openings and a second opening in the dielectric layer to expose portions of the contact plugs and a portion of the gate electrode respectively; performing a pre-clean process such as applying an ozone-containing source to the exposed portions of the contact plugs and the gate electrode; performing a surface treatment to the first and second openings to passivate sidewalls of the first and second openings; forming a conductive layer to fill the first openings and the second opening in a same deposition process by using a same metal precursor; and performing a planarization process.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Sheng-Tsung Wang, Huan-Chieh Su, Chih-Hao Wang, Meng-Huan Jao
  • Publication number: 20250087480
    Abstract: Embodiments of the present disclosure provide a plasma-enhanced atomic layer deposition apparatus and a method thereof. The apparatus includes a precursor supply device communicating with gas inlet structures of two process chambers and configured to selectively provide a precursor or a purge gas to at least one of the two process chambers, a reaction gas supply device communicating with the gas inlet structures of the two process chambers and configured to selectively provide a reaction gas to at least one of the two process chambers, a radio frequency device connected to the two process chambers and configured to selectively output radio frequency power to at least one of the two process chambers, and a pressure adjustment device communicating with exhaust openings of the two process chambers and configured to independently control chamber pressures of the two process chambers.
    Type: Application
    Filed: April 6, 2022
    Publication date: March 13, 2025
    Inventors: Haifeng QIN, Xiaoping SHI, Yunfeng LAN, Wenqiang ZHANG, Hao WANG, Xiaoyan REN
  • Patent number: 12249621
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first channel structures and second channel structures formed over the substrate. The semiconductor structure also includes a dielectric fin structure formed between the first channel structures and the second channel structures. In addition, the dielectric fin structure includes a core portion and first connecting portions connected to the core portion. The semiconductor structure also includes a gate structure including a first portion. In addition, the first portion of the gate structure is formed around the first channel structures and covers the first connecting portions of the dielectric fin structure.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: March 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guan-Lin Chen, Jung-Chien Cheng, Kuo-Cheng Chiang, Shi-Ning Ju, Chih-Hao Wang
  • Patent number: 12246931
    Abstract: The present invention provides a wafer transfer device.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: March 11, 2025
    Assignee: SHENYANG KINGSEMI Co., Ltd.
    Inventors: Tianyao Wu, Hao Wang, Xinglong Chen, Tao Miao
  • Publication number: 20250081594
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.
    Type: Application
    Filed: November 20, 2024
    Publication date: March 6, 2025
    Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shang-Wen CHANG, Ching-Wei TSAI, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20250077000
    Abstract: This application relates to the stylus field, provides a stylus and an electronic device assembly. The stylus includes a main circuit board, a pressure sensing module, and a first flexible printed circuit. The main circuit board includes a pressure sensing chip; the pressure sensing module includes a pressure strain collection element; one end of the first flexible printed circuit is electrically connected to the pressure strain collection element, and the other end of the first flexible printed circuit is electrically connected to the main circuit board for communication between the pressure sensing chip and the pressure strain collection element. The stylus may be further configured to transmit a first coded signal and a second coded signal. The second coded signal of a coding chip is transmitted by using a second flexible printed circuit.
    Type: Application
    Filed: November 3, 2022
    Publication date: March 6, 2025
    Inventors: Hao Wang, Tengfei Leng
  • Publication number: 20250076600
    Abstract: Embodiments of the present application disclose a photonic chip, a LiDAR, and a mobile device. The photonic chip has a substrate, a cladding layer, a first coupler, a first beam splitter, an emitting waveguide module, and a first optical adjusting monitoring module. The first beam splitter includes a first port, a second port, a third port, and a fourth port. The first beam splitter is configured to output the optical signal input through the first port through the third port and the fourth port, and to output the optical signal input through the third port through the first port and the second port. The first optical adjusting monitoring module includes a first photodetector. Monitors the optical power of the return light received by the emitting waveguide module through the first optical adjusting monitoring module integrated on the photonic chip, making the process more time-saving and labor-saving.
    Type: Application
    Filed: August 26, 2024
    Publication date: March 6, 2025
    Applicant: SUTENG INNOVATION TECHNOLOGY CO., LTD.
    Inventors: Hao Wang, Jiawen Liao, Penghui Dong, Jing Wang