Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: A package structure includes a thermal dissipation structure including a substrate, a first encapsulant laterally covering the substrate, a die disposed on the substrate and including a sensing region, a second encapsulant laterally covering the die, and a redistribution structure disposed on the die and the second encapsulant. An outer sidewall of the second encapsulant is laterally offset from an outer sidewall of the first encapsulant. The die is electrically coupled to the substrate through the redistribution structure, and the redistribution structure includes a hollow region overlying the sensing region of the die.

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.

Abstract: A heterogeneous integration chip of a micro fluid actuator is disclosed and includes a first substrate, a first insulation layer, a first conductive layer, a piezoelectric layer, a second conductive layer, a second substrate, a control element, a perforated trench and a conductor. The first substrate includes a first chamber. The first insulation layer is disposed on the first substrate. The first conductive layer is disposed on the first insulation layer and includes an electrode pad. The piezoelectric layer and the second conductive layer are stacked on the first conductive layer sequentially. The second substrate is assembled to the first substrate through a bonding layer to define a second chamber and includes an orifice, a fluid flowing channel and a third chamber. The control element is disposed in the second substrate. The perforated trench filled with the conductor is penetrated from the electrode pad to the second substrate.

Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.

Abstract: A package structure including a semiconductor die, a redistribution layer structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution layer structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution layer structure includes a backside dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the backside dielectric layer and the inter-dielectric layers. The electronic device is disposed over the backside dielectric layer and electrically connected to an outermost redistribution conductive layer among the redistribution conductive layers, wherein the outermost redistribution conductive layer is embedded in the backside dielectric layer, and the backside dielectric layer comprises a ring-shaped recess covered by the outermost redistribution conductive layer.

Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.

Abstract: A semiconductor device package structure is provided, including a redistribution structure, a first semiconductor device, a second semiconductor device, a bridge die, a first conductive bump, and a second conductive bump bumps, a third conductive bumps, and a first solder material. The first semiconductor device is disposed on a first side of the redistribution structure, the second semiconductor device and the bridge die are disposed on a second side opposite to the first side. The first conductive bump is disposed on the first semiconductor device, the second conductive bump is disposed on the second side of the redistribution structure and the third conductive bump is disposed on the second semiconductor device. The first solder material is electrically connected between the second conductive bump and the third conductive bump, and the redistribution structure is electrically connected between the first conductive bump and the second conductive bump.

Abstract: An imaging lens assembly module includes an imaging lens assembly and a variable aperture module. The imaging lens assembly has an optical axis. The variable aperture module includes a light blocking sheet set, a fixed element, a movable element, and an annular light blocking portion. The light blocking sheet set includes at least two light blocking sheets, wherein the at least two light blocking sheets are mutually stacked along a circumferential direction surrounding the optical axis to form a variable aperture opening. The fixed element has a sidewall structure. The annular light blocking portion surrounds the optical axis to form a fixed aperture opening.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: The present disclosure relates to a method for forming a mark, a packaging method for a semiconductor device, and a semiconductor device having the mark, wherein the marking material is a polymer compound and the light transmittance of the marking material is less than 50%, which is suitable for forming the mark on the semiconductor device by laser sintering, and the marking material is sintered to make the resin cross-link and cure to form a cured product. In addition, in one embodiment, the cured product formed by the marking material can be used as a deflector to guide the flow of the underfill and control the flow rate of underfill, so as to effectively solve the problem of uneven flow rate of the underfill.

Abstract: Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.

Abstract: A semiconductor package includes an encapsulated semiconductor device, a backside redistribution structure, and a front side redistribution structure. The encapsulated semiconductor device includes an encapsulating material and a semiconductor device encapsulated by the encapsulating material. The backside redistribution structure is disposed on a backside of the encapsulated semiconductor device and includes a redistribution circuit layer and a first patterned dielectric layer. The redistribution circuit layer has a circuit pattern and a dummy pattern electrically insulated from the circuit pattern. The dummy pattern is overlapped with the semiconductor device from a top view of the semiconductor package. The first patterned dielectric layer is disposed on the redistribution circuit layer and includes a marking pattern disposed on the dummy pattern and revealing a part of the dummy pattern.

Abstract: An embedded circuit board made without gas bubbles or significant internal gaps according to a manufacturing method which is here disclosed comprises an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces, a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.

Abstract: A remote control system for gas detection and purification is disclosed and includes a remote control device, a gas detection module and a gas purification device. The remote control device includes a gas inlet and a gas outlet. The gas detection module is disposed in the remote control device and in communication with the gas outlet to detect the gas located in an indoor space. The gas detection module provides and outputs a gas detection datum, and the remote control device transmits an operation command via wireless transmission. The gas purification device is disposed in the indoor space and receives the operating instruction transmitted from the remote control device to be operated. When the gas purification device is under the activated state, the gas in the indoor space is purified, and the purification operation mode of the gas purification device is adjusted according to the first gas detection datum.

Abstract: A device die including a first semiconductor die, a second semiconductor die, an anti-arcing layer and a first insulating encapsulant is provided. The second semiconductor die is stacked over and electrically connected to the first semiconductor die. The anti-arcing layer is in contact with the second semiconductor die. The first insulating encapsulant is disposed over the first semiconductor die and laterally encapsulates the second semiconductor die. Furthermore, methods for fabricating device dies are provided.

Abstract: A dynamic aperture module includes a blade set and a driving portion. The blade set includes a plurality of blades, which are disposed around an optical axis to form a light through hole and rotatable for adjusting the light through hole. The driving portion includes a rotating element, at least one magnet and at least one coil. The rotating element corresponds to the blades and is configured to drive the blades to rotate, so that a dimension of the light through hole is variable. The magnet includes four polarities. The polarities of the magnet are relatively distributed along a direction surrounding the optical axis and a direction parallel to the optical axis, respectively. The coil corresponds to the magnet, and one of the magnet and the coil is disposed on the rotating element. The magnet and the coil are disposed along the direction parallel to the optical axis.