Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: A blood pressure device includes a first blood pressure measuring device, a second blood pressure measuring device, and a controller. The first blood pressure measuring device is to be worn on a first position of a wrist so as to obtain a first blood pressure information of the first position. The second blood pressure measuring device is to be worn on a second position of the wrist so as to obtain a second blood pressure information of the second position. The controller is electrically coupled to the first blood pressure measuring device and the second blood pressure measuring device so as to adjust tightness between the expanders and the user's skin, respectively. The controller receives, processes, and calculates a pulse transit time between the first blood pressure information and the second blood pressure information, and the controller obtains at least one blood pressure value based on the pulse transit time.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: Crystalline 4-((L-valyl)oxy)butanoic acid, methods of preparing crystalline 4-((L-valyl)oxy)butanoic acid, pharmaceutical compositions of crystalline 4-((L-valyl)oxy)butanoic acid, and methods of treatment using crystalline 4-((L-valyl)oxy)butanoic acid are disclosed.

Abstract: An imaging lens module includes a casing, an imaging lens disposed to the casing, a lens carrier supporting the image lens, an elastic element connected to the lens carrier to provide the lens carrier with a translational degree of freedom along an optical axis, a frame connected to the elastic element such that the lens carrier is movable along the optical axis with respect to the frame, a variable through hole module coupled to the imaging lens and having a light passable hole with a variable aperture size, and a wiring assembly including a fixed wiring part at least partially located closer to the opening than the elastic element and a movable wiring part electrically connected to the fixed wiring part and the variable through hole module. The optical axis passes through lens elements of the imaging lens and the center of the variable through hole module.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: Embodiments include a memory device with an improved calibration circuit. Memory device input/output pins include delay lines for adjusting the delay in each memory input/output signal path. The delay adjustment circuitry includes digital delay lines for adjusting this delay. Further, each digital delay line is calibrated via a digital delay line locked loop which enables adjustment of the delay through the digital delay line in fractions of a unit interval across variations due to differences in manufacturing process, operating voltage, and operating temperature. The disclosed techniques calibrate the digital delay lines by measuring both the high phase and the low phase of the clock signal. As a result, the disclosed techniques compensate for duty cycle distortion by combining the calibration results from both phases of the clock signal. The disclosed techniques thereby result in lower calibration error relative to approaches that measure only one phase of the clock signal.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: A method of manufacturing a semiconductor package includes the following steps. A backside redistribution structure is formed, wherein the backside redistribution structure comprises a first dielectric layer, and a redistribution metal layer over the first dielectric layer and comprising a dummy pattern. A semiconductor device is provided over the backside redistribution structure, wherein an active surface of the semiconductor device faces away from the backside redistribution structure, the semiconductor device is electrically insulated from the dummy pattern and overlapped with the dummy pattern from a top view of the semiconductor package. A front side redistribution structure is formed over the semiconductor device, wherein the front side redistribution structure is electrically connected to the semiconductor device. A patterning process is performed on the first dielectric layer to form a marking pattern opening exposing a part of the dummy pattern.

Abstract: An antenna device, a positioning system and a positioning method are provided. The positioning method includes: dispersedly arranging a plurality of receivers to form a target area, in which each of the receivers includes the antenna device; receiving a wireless signal from the target area through the antenna device, and generating a difference signal strength and a sum signal strength; calculating, for each of the receivers, a sum-difference ratio between the difference signal strength and the sum signal strength, and estimating a corresponding one of estimated incident angles according to the sum-difference ratio and a comparison table; executing, in response to obtaining the estimated incident angles corresponding to the receivers, a positioning algorithm according to the estimated incident angles, so as to generate a plurality of possible positions; and executing an optimization algorithm to calculate a best estimated position of the possible positions.

Abstract: A semiconductor structure includes a die and a first connector. The first connector is disposed on the die. The first connector includes a first connecting housing, a first connecting element and a first connecting portion. The first connecting element is electrically connected to the die and disposed at a first side of the first connecting housing. The first connecting portion is disposed at a second side different from the first side of the first connecting housing, wherein the first connecting portion is one of a hole and a protrusion with respect to a surface of the second side of the first connecting housing.

Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.

Abstract: A method can include receiving a low-resolution (LR) image, extracting a first feature embedding from the LR image, performing a first upsampling to the LR image by a first upsampling factor to generate a upsampled image, receiving a LR coordinate of a pixel within the LR image and a first cell size of the LR coordinate, generating a first residual image based on the first feature embedding, the LR coordinate, and the first cell size of the LR coordinate using a local implicit image function, and generating a first high-resolution (HR) image by combining the first residual image and the upsampled image via element-wise addition.

Abstract: A semiconductor package includes a first redistribution structure, a second redistribution structure, a first die, a first encapsulant, a second die, a second encapsulant, conductive connectors, and a third die. The second redistribution structure is over the first redistribution structure. The first die is located between the first redistribution structure and the second redistribution structure. The first encapsulant laterally encapsulates the first die. The second die is disposed on and electrically connected to the second redistribution structure. The second encapsulant laterally encapsulates the second die. The conductive connectors surround the second die and are embedded in the second encapsulant. The third die is disposed over the second die. The third die is in physical contact with the second encapsulant and the conductive connectors.

Abstract: A device die including a first semiconductor die, a second semiconductor die, an anti-arcing layer and a first insulating encapsulant is provided. The second semiconductor die is stacked over and electrically connected to the first semiconductor die. The anti-arcing layer is in contact with the second semiconductor die. The first insulating encapsulant is disposed over the first semiconductor die and laterally encapsulates the second semiconductor die. Furthermore, methods for fabricating device dies are provided.

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die laterally covered by an insulating encapsulation, a first redistribution structure overlying the insulating encapsulation and a back surface of the semiconductor die, a second redistribution structure underlying the insulating encapsulation and an active surface of the semiconductor die opposite to the back surface, active through insulating vias (TIVs) penetrating through the insulating encapsulation, and dummy features. The semiconductor die is electrically coupled to the first redistribution structure through the second redistribution structure and the active TIVs. Each of the dummy features includes a dummy TIV laterally covered by the insulating encapsulation, the dummy TIVs are disposed along package edges in a top view, and the dummy features are electrically floating.

Abstract: A semiconductor device includes a first redistribution structure, a first semiconductor package, a second semiconductor package, an encapsulation layer, a first thermal interface material (TIM) layer, and a second TIM layer. The first semiconductor package and the second semiconductor package are respectively disposed on the first redistribution structure and laterally disposed aside with each other. The encapsulation layer encapsulates and surrounds the first semiconductor package and the second semiconductor package. The first semiconductor package and the second semiconductor package are respectively exposed from the encapsulation layer. The first TIM layer and the second TIM layer are respectively disposed on back surfaces of the first semiconductor package and the second semiconductor package. A top surface of the first TIM layer and a top surface of the second TIM layer are coplanar with a top surface of the encapsulation layer.

Abstract: Disclosed are a stamping method and a deep-drawing die for an aluminum alloy liner of a large-volume hydrogen storage cylinder, which solve that technical problem of low production efficiency of processing the aluminum alloy liner of the large-volume hydrogen storage cylinder by adopting strong spin and thinning of an aluminum tube in the prior art. The stamping method includes heating and stamping an aluminum ingot into a cup-shaped rough blank, then cold deep drawing the cup-shaped rough blank for thinning and lengthening into an aluminium alloy liner, and the deep-drawing die includes terrace die and thinning dies.