Patents by Inventor Hao-Yu Chen
Hao-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100200923Abstract: A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized.Type: ApplicationFiled: April 13, 2010Publication date: August 12, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hao-Yu Chen, Yee-Chia Yeo, Fu-Liang Yang
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Publication number: 20100176424Abstract: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.Type: ApplicationFiled: March 25, 2010Publication date: July 15, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yee-Chia Yeo, Ping-Wei Wang, Hao-Yu Chen, Fu-Liang Yang, Chenming Hu
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Patent number: 7728360Abstract: A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized.Type: GrantFiled: December 6, 2002Date of Patent: June 1, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hao-Yu Chen, Yee-Chia Yeo, Fu-Liang Yang
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Patent number: 7701008Abstract: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.Type: GrantFiled: June 5, 2006Date of Patent: April 20, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yee-Chia Yeo, Ping-Wei Wang, Hao-Yu Chen, Fu-Liang Yang, Chenming Hu
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Patent number: 7638376Abstract: A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.Type: GrantFiled: January 12, 2007Date of Patent: December 29, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Kuo Wen, Chien-Chao Huang, Hao-Yu Chen, Fu-Liang Yang, Hsun-Chih Tsao
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Patent number: 7635632Abstract: A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction arid activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.Type: GrantFiled: January 3, 2007Date of Patent: December 22, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yee-Chia Yeo, Hao-Yu Chen, Fu-Liang Yang, Chenming Hu
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Patent number: 7608515Abstract: A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A silicon layer may be epitaxially grown over the diffusion barrier in the recessed regions. Thereafter, the recessed regions may be filled and doped with a semiconductor or semiconductor alloy material. In an embodiment, a semiconductor alloy material, such as silicon carbon, is selected to induce a tensile stress in the channel region for an NMOS device, and a semiconductor alloy material, such as silicon germanium, is selected to induce a compressive stress in the channel region for a PMOS device.Type: GrantFiled: February 14, 2006Date of Patent: October 27, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yu Chen, Shui-Ming Cheng
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Patent number: 7585711Abstract: A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semiconductor region and an upper semiconductor region overlying the insulator region; patterning the upper semiconductor region and insulator region to form a MOS active region; forming an MOS device comprising a gate structure and a channel region on the MOS active region; and, carrying out an oxidation process to oxidize a portion of the upper semiconductor region to produce a strain in the channel region.Type: GrantFiled: August 2, 2006Date of Patent: September 8, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hao-Yu Chen, Fu-Liang Yang
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Patent number: 7485929Abstract: Differentially strained active regions for forming strained channel semiconductor devices and a method of forming the same, the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semiconductor region and an upper semiconductor region overlying the insulator region; forming a doped area of the insulator region underlying a subsequently formed NMOS active region; patterning the upper semiconductor region to form the NMOS active region and a PMOS active region; carrying out a thermal oxidation process to produce a differential-volume expansion in the PMOS active region with respect to the NMOS active region; forming recessed areas comprising the insulator region adjacent either side of the PMOS active region; and, removing layers overlying the upper semiconductor region to produce differentially strained regions comprising the PMOS and NMOS active regions.Type: GrantFiled: September 15, 2006Date of Patent: February 3, 2009Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Hao-Yu Chen, Fu-Liang Yang
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Publication number: 20080237717Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.Type: ApplicationFiled: April 25, 2008Publication date: October 2, 2008Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
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Patent number: 7423323Abstract: A device having a raised segment, and a manufacturing method for same. An SOI wafer is provided having a substrate, an insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the insulating layer. The semiconductor material is patterned to form a mesa structure. The wafer is annealed to form a raised segment on the mesa structure.Type: GrantFiled: February 23, 2005Date of Patent: September 9, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yu Chen, Yee-Chia Yeo, Fu-Liang Yang, Chenming Hu
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Publication number: 20080185650Abstract: A method and system is disclosed for providing access to the body of a FinFET device. In one embodiment, a FinFET device for characterization comprises an active fin comprising a source fin, a depletion fin, and a drain fin; a side fin extending from the depletion fin and coupled to a body contact for providing access for device characterization; and a gate electrode formed over the depletion fin and separated therefrom by a predetermined dielectric layer, wherein the gate electrode and the dielectric layer thereunder have a predetermined configuration to assure the source and drain fins are not shorted.Type: ApplicationFiled: February 1, 2007Publication date: August 7, 2008Inventors: Hao-Yu Chen, Chang-Yun Chang, Cheng-Chuan Huang, Fu-Liang Yang
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Publication number: 20080171419Abstract: A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Kuo Wen, Chien-Chao Huang, Hao-Yu Chen, Fu-Liang Yang, Hsun-Chih Tsao
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Patent number: 7382023Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.Type: GrantFiled: March 29, 2005Date of Patent: June 3, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
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Publication number: 20080061379Abstract: An MOS device includes a gate stack overlying a semiconductor substrate and a graded source/drain region adjacent to the gate stack. The graded source/drain region includes a first grade having a first depth, a second grade spaced further apart from a channel region than the first grade, and a third grade spaced further apart from the channel region than the second grade. The depth of the second grade is between the respective depths of the first and the third grades. The MOS device further includes a silicide region on a top surface of the source/drain region wherein the silicide region has an inner edge substantially aligned with an inner edge of the third grade, and a graded gate spacer comprising an inner portion on a sidewall of the gate stack and an outer portion on a sidewall of the inner portion.Type: ApplicationFiled: September 8, 2006Publication date: March 13, 2008Inventors: Hao-Yu Chen, Shui-Ming Cheng, Ken-Ichi Goto
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Publication number: 20080029815Abstract: A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semiconductor region and an upper semiconductor region overlying the insulator region; patterning the upper semiconductor region and insulator region to form a MOS active region; forming an MOS device comprising a gate structure and a channel region on the MOS active region; and, carrying out an oxidation process to oxidize a portion of the upper semiconductor region to produce a strain in the channel region.Type: ApplicationFiled: August 2, 2006Publication date: February 7, 2008Inventors: Hao-Yu Chen, Fu-Liang Yang
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Publication number: 20070246798Abstract: An inductive device including an inductor coil located over a substrate, at least one electrically insulating layer interposing the inductor coil and the substrate, and a plurality of current interrupters each extending into the substrate, wherein a first aggregate outer boundary of the plurality of current interrupters substantially encompasses a second aggregate outer boundary of the inductor coil.Type: ApplicationFiled: June 25, 2007Publication date: October 25, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Andrew Yeh, Alex Chang, Sung-Pi Tseng, Chang-Yun Chang, Hao-Yu Chen, Fu-Liang Yang
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Publication number: 20070190731Abstract: A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A silicon layer may be epitaxially grown over the diffusion barrier in the recessed regions. Thereafter, the recessed regions may be filled and doped with a semiconductor or semiconductor alloy material. In an embodiment, a semiconductor alloy material, such as silicon carbon, is selected to induce a tensile stress in the channel region for an NMOS device, and a semiconductor alloy material, such as silicon germanium, is selected to induce a compressive stress in the channel region for a PMOS device.Type: ApplicationFiled: February 14, 2006Publication date: August 16, 2007Inventors: Hao-Yu Chen, Shui-Ming Cheng
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Patent number: 7230270Abstract: In a method of forming a double gate device, a buried insulating layer having a thickness of less than about 30 nm is formed on a first substrate. A second substrate is formed on the buried insulating layer. A pad layer is formed over the second substrate. A mask layer is formed over the pad layer. A first trench is formed extending through the pad layer, second substrate, buried insulating layer and into the first substrate. The first trench is filled with a first isolation. A second trench is formed in the first isolation and filled with a conductive material. An MOS transistor is formed on the second substrate. A bottom gate is formed under the buried insulating layer and self-aligned to the top gate formed on the second substrate.Type: GrantFiled: November 24, 2004Date of Patent: June 12, 2007Assignee: Taiwan Semiconductor Manfacturing Company, Ltd.Inventors: Hao-Yu Chen, Ju-Wang Hsu, Baw-Ching Perng, Fu-Liang Yang
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Publication number: 20070111454Abstract: A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction arid activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.Type: ApplicationFiled: January 3, 2007Publication date: May 17, 2007Inventors: Yee-Chia Yeo, Hao-Yu Chen, Fu-Liang Yang, Chenming Hu