Abstract: An electron ptychography method and an electron ptychography apparatus for automatically correcting a mistilt of a zone axis of a sample.

Abstract: A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes presetting a programming mode of a plurality of first type physical erasing units as a first programming mode, and presetting a programming mode of a plurality of second type physical erasing units as a second programming mode. The method also includes obtaining a change parameter according to usage parameters of the first type physical erasing units and the second type physical erasing units. The method further includes determining whether the change parameter matches a first change condition, and if the change parameter matches the first change condition, programming a write-data into the second type physical erasing unit by using the first programming mode.

Abstract: A speaker diaphragm structure is installed inside a sound generator device which comprises a frame, a speaker diaphragm structure installed within the frame and a suspension edge whose inner perimeter is connected to the speaker diaphragm structure and whose outer perimeter is connected to the frame; herein the speaker diaphragm structure includes a diaphragm body and a composite material layer, in which the composite material layer is used for bonding onto the surface of the diaphragm body or attaching within the diaphragm body; moreover, the composite material layer is composed of one or more types of tetrapyrrole compounds as well as one or more types of metal ions; additionally, the composite material layer has a thickness smaller than the thickness of the diaphragm body, and is mainly applied to provide the performance effect of sound quality modifications.

Abstract: A method for triggering a registrar protocol interaction. The method includes: receiving, by an access point, a probe request sent by at least one station, where the probe request includes an identifier of the access point; determining, by the access point, a first station in the at least one station according to the probe request sent by the at least one station, where the identifier included in the probe request sent by the first station matches an identifier of the access point, and a signal strength of the probe request sent by the first station is greater than a signal strength threshold; and automatically triggering, by the access point, a registrar protocol interaction with the first station.

Abstract: A memory management method is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a plurality of commands from a host system; counting a newest idle time corresponding to the commands and a past average command-receiving-time-interval corresponding to the commands; and dynamically changing a work mode of a memory storage device from a first work mode to a second work mode if the newest idle time is larger than a first threshold value and the past average command-receiving-time-interval is larger than a second threshold value. Therefore, a power consumption of the memory storage device can be reduced and a work mode of the memory storage device may not be changed too frequently.

Abstract: A speaker diaphragm structure is installed inside a sound generator device which comprises a frame, a speaker diaphragm structure installed within the frame and a suspension edge whose inner perimeter is connected to the speaker diaphragm structure and whose outer perimeter is connected to the frame; herein the speaker diaphragm structure includes a diaphragm body and a composite material layer, in which the composite material layer is used for bonding onto the surface of the diaphragm body or attaching within the diaphragm body; moreover, the composite material layer is composed of one or more types of tetrapyrrole compounds as well as one or more types of metal ions; additionally, the composite material layer has a thickness smaller than the thickness of the diaphragm body, and is mainly applied to provide the performance effect of sound quality modifications.

Abstract: A method for triggering a registrar protocol interaction. The method includes: receiving, by an access point, a probe request sent by at least one station, where the probe request includes an identifier of the access point; determining, by the access point, a first station in the at least one station according to the probe request sent by the at least one station, where the identifier included in the probe request sent by the first station matches an identifier of the access point, and a signal strength of the probe request sent by the first station is greater than a signal strength threshold; and automatically triggering, by the access point, a registrar protocol interaction with the first station.

Abstract: A mapping table updating method, a memory control circuit unit and a memory storage device. The method includes: receiving a first data corresponding to a first logical address from a host system; loading a first logical address-physical address mapping table according to the first logical address; sending a command sequence to a rewritable non-volatile memory module; in the process of writing the first data into a first physical programming unit according to the command sequence by a control circuit of the rewritable non-volatile memory module, updating the first logical address-physical address mapping table; and after writing the first data into the first physical programming unit by the control circuit, storing the updated first logical address-physical address table back to the rewritable non-volatile memory module.

Abstract: A method for triggering a registrar protocol interaction. The method includes: receiving, by an access point, a probe request sent by at least one station, where the probe request includes an identifier of the access point; determining, by the access point, a first station in the at least one station according to the probe request sent by the at least one station, where the identifier included in the probe request sent by the first station matches an identifier of the access point, and a signal strength of the probe request sent by the first station is greater than a signal strength threshold; and automatically triggering, by the access point, a registrar protocol interaction with the first station.

Abstract: A memory management method is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a plurality of commands from a host system; counting a newest idle time corresponding to the commands and a past average command-receiving-time-interval corresponding to the commands; and dynamically changing a work mode of a memory storage device from a first work mode to a second work mode if the newest idle time is larger than a first threshold value and the past average command-receiving-time-interval is larger than a second threshold value. Therefore, a power consumption of the memory storage device can be reduced and a work mode of the memory storage device may not be changed too frequently.

Abstract: A mapping table updating method, a memory control circuit unit and a memory storage device. The method includes: receiving a first data corresponding to a first logical address from a host system; loading a first logical address-physical address mapping table according to the first logical address; sending a command sequence to a rewritable non-volatile memory module; in the process of writing the first data into a first physical programming unit according to the command sequence by a control circuit of the rewritable non-volatile memory module, updating the first logical address-physical address mapping table; and after writing the first data into the first physical programming unit by the control circuit, storing the updated first logical address-physical address table back to the rewritable non-volatile memory module.

Abstract: The present invention relates to a memory management method, memory control circuit unit, and a memory storage device. The method includes: transmitting temporary data from a buffer memory to a register of a first memory plane; releasing a first storage space of the buffer memory, wherein the first storage space is configured to store the temporary data; performing a first operation to a second memory plane by using the first storage space; and after finishing the first operation performed on the second memory plane, reloading the temporary data from the register of the first memory plane to the first storage space of the buffer memory, wherein operations performed on the first memory plane and the second memory plane are asynchronous operations.

Abstract: A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes presetting a programming mode of a plurality of first type physical erasing units as a first programming mode, and presetting a programming mode of a plurality of second type physical erasing units as a second programming mode. The method also includes obtaining a change parameter according to usage parameters of the first type physical erasing units and the second type physical erasing units. The method further includes determining whether the change parameter matches a first change condition, and if the change parameter matches the first change condition, programming a write-data into the second type physical erasing unit by using the first programming mode.

Abstract: A relaxation oscillator for generating a low temperature coefficient (LTC) clock signal includes a reference voltage generator and an oscillator. The reference voltage generator generates an LTC current and a bandgap reference voltage. The reference voltage generator includes positive temperature coefficient (PTC) resistors to compensate for the effects of temperature variations. The oscillator receives the LTC current and the bandgap reference voltage, and generates a clock signal. In another embodiment, the reference voltage generator generates a charge current that varies with temperature. The oscillator receives the charge current and generates first and second output signals. Set and reset comparators include PTC resistors that determine the gains of the set and reset comparators. The PTC resistors compensate for variation in the first and second output signals due to the temperature variations by varying the gains of the set and reset comparators.

Abstract: A mapping table loading method and a memory storage apparatus are provided. The method includes: receiving a plurality of first read commands comprising a plurality of first logical units; executing a first logical-physical mapping table pre-loading operation to read a plurality of mapping information corresponding to the first logical units in a logical-physical mapping table from a rewritable non-volatile memory module to a first buffer area of a buffer memory according to a first executing sequence of the first read commands if the first logical units are not continuous logical addresses; and reading data belonging to the first logical units from physical erasing units to the first buffer area according to the mapping information of the first logical units, and replacing the mapping information of the first logical units in the first buffer area by the data belonging to the first logical units.

Abstract: A mapping table loading method and a memory storage apparatus are provided. The method includes: receiving a plurality of first read commands comprising a plurality of first logical units; executing a first logical-physical mapping table pre-loading operation to read a plurality of mapping information corresponding to the first logical units in a logical-physical mapping table from a rewritable non-volatile memory module to a first buffer area of a buffer memory according to a first executing sequence of the first read commands if the first logical units are not continuous logical addresses; and reading data belonging to the first logical units from physical erasing units to the first buffer area according to the mapping information of the first logical units, and replacing the mapping information of the first logical units in the first buffer area by the data belonging to the first logical units.

Abstract: A relaxation oscillator for generating a low temperature coefficient (LTC) clock signal includes a reference voltage generator and an oscillator. The reference voltage generator generates an LTC current and a bandgap reference voltage. The reference voltage generator includes positive temperature coefficient (PTC) resistors to compensate for the effects of temperature variations. The oscillator receives the LTC current and the bandgap reference voltage, and generates a clock signal. In another embodiment, the reference voltage generator generates a charge current that varies with temperature. The oscillator receives the charge current and generates first and second output signals. Set and reset comparators include PTC resistors that determine the gains of the set and reset comparators. The PTC resistors compensate for variation in the first and second output signals due to the temperature variations by varying the gains of the set and reset comparators.

Abstract: The present invention relates to a memory management method, memory control circuit unit, and a memory storage device. The method includes: transmitting temporary data from a buffer memory to a register of a first memory plane; releasing a first storage space of the buffer memory, wherein the first storage space is configured to store the temporary data; performing a first operation to a second memory plane by using the first storage space; and after finishing the first operation performed on the second memory plane, reloading the temporary data from the register of the first memory plane to the first storage space of the buffer memory, wherein operations performed on the first memory plane and the second memory plane are asynchronous operations.

Abstract: A rail-to-rail comparator circuit includes NMOS and PMOS differential input stages with associated loads that are coupled to a shared-load stage. The shared-load stage is coupled to an output stage that includes two active devices. By sharing the load stage between the two input stages, the comparator has a relatively small circuit area, low power draw, and low propagation delay with rail-to-rail input common-mode voltage range.

Abstract: A data writing method for writing data into a physical erasing unit and a memory controller and a memory storage apparatus using the data writing method are provided. The method includes dividing the data into a plurality of information frames in a unit of one physical programming unit. The method also includes writing the information frames in sequence into at least one physical programming unit constituted by memory cells disposed on at least one first word line and programming the storage state of memory cells disposed on at least one second word line following the first word line to an auxiliary pattern. Accordingly, the method effectively prevents data stored in the physical erasing unit, which is not full of data, from being lost due to a high temperature.