Patents by Inventor Hardwell Chibvongodze

Hardwell Chibvongodze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11222954
    Abstract: A three-dimensional memory device includes an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers located over a substrate, a plurality of drain-select-level electrodes that are laterally spaced apart from each other overlying the alternating stack, memory stack structures containing a respective vertical semiconductor channel laterally surrounded by a respective memory film and vertically extending through the alternating stack and the plurality of drain-select-level electrodes, inter-select-gate electrodes located between a respective neighboring pair of the drain-select-level electrodes, and inter-select-gate dielectrics located between each of the inter-select-gate electrodes and a neighboring one of the drain-select-level electrodes. The inter-select-gate electrodes are not electrically connected to the drain-select-level electrodes.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: January 11, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Hardwell Chibvongodze, Masatoshi Nishikawa
  • Publication number: 20210375847
    Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Inventors: Hardwell CHIBVONGODZE, Zhixin CUI, Rajdeep GAUTAM
  • Patent number: 11189335
    Abstract: A three-dimensional (3D) memory is provided, including a memory array chip and a complementary metal-oxide semiconductor (CMOS) chip disposed on the memory array chip. The memory chip provides double write/read throughput and includes a lower region with a lower array of memory cells, lower word lines, and a lower bit line, while an upper region includes an upper array of memory cells, upper word lines, and an upper bit line. A source line is disposed between the lower and upper regions and is connected to both the lower array of memory cells and the upper array of memory cells.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: November 30, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Masatoshi Nishikawa, Hardwell Chibvongodze, Ken Oowada
  • Publication number: 20210305384
    Abstract: A three-dimensional memory device includes an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers located over a substrate, a plurality of drain-select-level electrodes that are laterally spaced apart from each other overlying the alternating stack, memory stack structures containing a respective vertical semiconductor channel laterally surrounded by a respective memory film and vertically extending through the alternating stack and the plurality of drain-select-level electrodes, inter-select-gate electrodes located between a respective neighboring pair of the drain-select-level electrodes, and inter-select-gate dielectrics located between each of the inter-select-gate electrodes and a neighboring one of the drain-select-level electrodes. The inter-select-gate electrodes are not electrically connected to the drain-select-level electrodes.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Zhixin CUI, Hardwell CHIBVONGODZE, Masatoshi NISHIKAWA
  • Patent number: 11081185
    Abstract: A memory device is disclosed configured to share word line switches (WLSW) between each word line of two adjacent erase blocks. The word lines are driven from both sides of the memory array to reduces resistive-capacitive (RC) loading during pre-charge/ramp-up periods and during discharge/ramp-down periods for various storage operations. The dual-sided driving of signals combines with synergistic erase block size management to lower read latency (tR) for non-volatile memory media.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 3, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Patent number: 11069410
    Abstract: First alternating stacks of first insulating strips and first spacer material strips is formed in a first device region, second alternating stacks of second insulating strips and second spacer material strips are formed in a second device region. Each of the first line trenches is filled with a respective laterally alternating sequence of memory stack structures and first dielectric pillar structures to form a three-dimensional NAND memory. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements. Each of the second line trenches with a respective laterally alternating sequence of active region assemblies of lateral field effect transistors and second dielectric pillar structures to form a three-dimensional NOR memory. Each of the active region assemblies includes a source pillar, a drain pillar, and a tubular channel region. The spacer material strips include, or are subsequently replaced with, electrically conductive strips.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: July 20, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Hardwell Chibvongodze, Rajdeep Gautam
  • Publication number: 20210173559
    Abstract: A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes logically grouping memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 10, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Masatoshi Nishikawa, Hardwell Chibvongodze
  • Patent number: 11024385
    Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module includes a first semiconductor die comprising first non-volatile memory cells, a second semiconductor die comprising second non-volatile memory cells, and a third semiconductor die comprising control circuitry. The first, the second and the third semiconductor die are bonded together. The control circuitry is configured to control memory operations in the first memory cells in parallel with the second memory cells.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 1, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Publication number: 20210142841
    Abstract: A three-dimensional (3D) memory is provided, including a memory array chip and a complementary metal-oxide semiconductor (CMOS) chip disposed on the memory array chip. The memory chip provides double write/read throughput and includes a lower region with a lower array of memory cells, lower word lines, and a lower bit line, while an upper region includes an upper array of memory cells, upper word lines, and an upper bit line. A source line is disposed between the lower and upper regions and is connected to both the lower array of memory cells and the upper array of memory cells.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Masatoshi Nishikawa, Hardwell Chibvongodze, Ken Oowada
  • Patent number: 10978152
    Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 13, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rajdeep Gautam, Hardwell Chibvongodze, Ken Oowada
  • Patent number: 10971231
    Abstract: Systems and methods for reducing program disturb when programming portions of a memory array are described. A memory array may include a first set of NAND strings and a second set of NAND strings that share a common bit line that is connected to the drain-side end of drain-side select gates of the NAND strings and/or share a common source-side select gate line that connects to the gates of source-side select gates of the NAND strings. During programming of the first set of NAND strings a first pass voltage (e.g., 7V) may be applied to unselected word lines of the memory array and subsequently during programming of the second set of NAND strings a second pass voltage (e.g., 9V) greater than the first pass voltage may be applied to the unselected word lines of the memory array.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 6, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rajdeep Gautam, Hardwell Chibvongodze, Ken Oowada
  • Publication number: 20210082506
    Abstract: Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 18, 2021
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Patent number: 10878907
    Abstract: Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: December 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Publication number: 20200402587
    Abstract: A memory device is disclosed configured to share word line switches (WLSW) between each word line of two adjacent erase blocks. The word lines are driven from both sides of the memory array to reduces resistive-capacitive (RC) loading during pre-charge/ramp-up periods and during discharge/ramp-down periods for various storage operations. The dual-sided driving of signals combines with synergistic erase block size management to lower read latency (tR) for non-volatile memory media.
    Type: Application
    Filed: June 18, 2019
    Publication date: December 24, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Publication number: 20200388335
    Abstract: Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 10, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Patent number: 10854619
    Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: December 1, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
  • Publication number: 20200365210
    Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module includes a first semiconductor die comprising first non-volatile memory cells, a second semiconductor die comprising second non-volatile memory cells, and a third semiconductor die comprising control circuitry. The first, the second and the third semiconductor die are bonded together. The control circuitry is configured to control memory operations in the first memory cells in parallel with the second memory cells.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 19, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Patent number: 10839918
    Abstract: Boost converter in memory chip. A non-volatile memory including an in-chip boost converter includes: a first memory structure defines control circuitry disposed on a first substrate, and a first metal layers disposed adjacent the control circuitry, where the first metal layer couples elements of the control circuitry; and a second memory structure defines a memory array disposed on a second substrate, and a second metal layer disposed adjacent the memory array, where the first and second metal layers are bonded together by a permanent physical bond formed between the first and second metal layers; and a boost converter defining an inductor disposed in the first and second metal layers, and a transistor circuit disposed in the control circuitry. The non-volatile memory, where the inductor further defines a first terminal coupled to a voltage source, and a second terminal coupled to a load by way of a transistor circuit.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: November 17, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Publication number: 20200266182
    Abstract: A first memory die includes an array of first memory stack structures and first bit lines. A second memory die includes an array of second memory stack structures and second bit lines electrically connected to a respective subset of the second drain regions. A support die is provided, which includes a peripheral circuitry for operating the array of first memory stack structures and the array of second memory stack structures. The peripheral circuitry includes a plurality of sense amplifiers configured to make switchable electrical connections to a set of bit lines selected from the first bit lines and the second bit lines. The first memory die is bonded to the support die, and the second memory die is bonded to the first memory die. The peripheral circuitry in the support die may be shared between the first memory die and the second memory die.
    Type: Application
    Filed: February 14, 2019
    Publication date: August 20, 2020
    Inventors: Masatoshi NISHIKAWA, Hardwell CHIBVONGODZE
  • Patent number: 10741535
    Abstract: A first memory die includes an array of first memory stack structures and first bit lines. A second memory die includes an array of second memory stack structures and second bit lines electrically connected to a respective subset of the second drain regions. A support die is provided, which includes a peripheral circuitry for operating the array of first memory stack structures and the array of second memory stack structures. The peripheral circuitry includes a plurality of sense amplifiers configured to make switchable electrical connections to a set of bit lines selected from the first bit lines and the second bit lines. The first memory die is bonded to the support die, and the second memory die is bonded to the first memory die. The peripheral circuitry in the support die may be shared between the first memory die and the second memory die.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: August 11, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Hardwell Chibvongodze