Patents by Inventor Hardwell Chibvongodze
Hardwell Chibvongodze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10878907Abstract: Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.Type: GrantFiled: June 5, 2019Date of Patent: December 29, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Hardwell Chibvongodze, Masatoshi Nishikawa
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Publication number: 20200402587Abstract: A memory device is disclosed configured to share word line switches (WLSW) between each word line of two adjacent erase blocks. The word lines are driven from both sides of the memory array to reduces resistive-capacitive (RC) loading during pre-charge/ramp-up periods and during discharge/ramp-down periods for various storage operations. The dual-sided driving of signals combines with synergistic erase block size management to lower read latency (tR) for non-volatile memory media.Type: ApplicationFiled: June 18, 2019Publication date: December 24, 2020Applicant: SanDisk Technologies LLCInventors: Hardwell Chibvongodze, Masatoshi Nishikawa
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Publication number: 20200388335Abstract: Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.Type: ApplicationFiled: June 5, 2019Publication date: December 10, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Hardwell Chibvongodze, Masatoshi Nishikawa
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Patent number: 10854619Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.Type: GrantFiled: December 7, 2018Date of Patent: December 1, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
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Publication number: 20200365210Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module includes a first semiconductor die comprising first non-volatile memory cells, a second semiconductor die comprising second non-volatile memory cells, and a third semiconductor die comprising control circuitry. The first, the second and the third semiconductor die are bonded together. The control circuitry is configured to control memory operations in the first memory cells in parallel with the second memory cells.Type: ApplicationFiled: May 17, 2019Publication date: November 19, 2020Applicant: SanDisk Technologies LLCInventors: Hardwell Chibvongodze, Masatoshi Nishikawa
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Patent number: 10839918Abstract: Boost converter in memory chip. A non-volatile memory including an in-chip boost converter includes: a first memory structure defines control circuitry disposed on a first substrate, and a first metal layers disposed adjacent the control circuitry, where the first metal layer couples elements of the control circuitry; and a second memory structure defines a memory array disposed on a second substrate, and a second metal layer disposed adjacent the memory array, where the first and second metal layers are bonded together by a permanent physical bond formed between the first and second metal layers; and a boost converter defining an inductor disposed in the first and second metal layers, and a transistor circuit disposed in the control circuitry. The non-volatile memory, where the inductor further defines a first terminal coupled to a voltage source, and a second terminal coupled to a load by way of a transistor circuit.Type: GrantFiled: June 24, 2019Date of Patent: November 17, 2020Assignee: SanDisk Technologies LLCInventors: Hardwell Chibvongodze, Masatoshi Nishikawa
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Publication number: 20200266182Abstract: A first memory die includes an array of first memory stack structures and first bit lines. A second memory die includes an array of second memory stack structures and second bit lines electrically connected to a respective subset of the second drain regions. A support die is provided, which includes a peripheral circuitry for operating the array of first memory stack structures and the array of second memory stack structures. The peripheral circuitry includes a plurality of sense amplifiers configured to make switchable electrical connections to a set of bit lines selected from the first bit lines and the second bit lines. The first memory die is bonded to the support die, and the second memory die is bonded to the first memory die. The peripheral circuitry in the support die may be shared between the first memory die and the second memory die.Type: ApplicationFiled: February 14, 2019Publication date: August 20, 2020Inventors: Masatoshi NISHIKAWA, Hardwell CHIBVONGODZE
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Patent number: 10741535Abstract: A first memory die includes an array of first memory stack structures and first bit lines. A second memory die includes an array of second memory stack structures and second bit lines electrically connected to a respective subset of the second drain regions. A support die is provided, which includes a peripheral circuitry for operating the array of first memory stack structures and the array of second memory stack structures. The peripheral circuitry includes a plurality of sense amplifiers configured to make switchable electrical connections to a set of bit lines selected from the first bit lines and the second bit lines. The first memory die is bonded to the support die, and the second memory die is bonded to the first memory die. The peripheral circuitry in the support die may be shared between the first memory die and the second memory die.Type: GrantFiled: February 14, 2019Date of Patent: August 11, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Hardwell Chibvongodze
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Patent number: 10734080Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.Type: GrantFiled: December 7, 2018Date of Patent: August 4, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
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Publication number: 20200185039Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.Type: ApplicationFiled: December 7, 2018Publication date: June 11, 2020Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
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Publication number: 20200185397Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.Type: ApplicationFiled: December 7, 2018Publication date: June 11, 2020Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa, Naoki Ookuma, Takuya Ariki, Toru Miwa
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Patent number: 10629675Abstract: A semiconductor structure can include an alternating stack of insulating layers and electrically conductive layers located over a substrate, and capacitor pillar structures vertically extending through the first alternating stack. Each of the capacitor pillar structures can include a node dielectric and a semiconductor material portion that is laterally surrounded by the node dielectric. A first electrode layer of a capacitor includes the semiconductor material portions, and a second electrode layer of the capacitor includes the electrically conductive layers. Alternatively or additionally, a first dielectric fill material portion can extend through the alternating stack and can include a plurality of capacitor via cavities. A capacitor can be provided within the plurality of capacitor via cavities.Type: GrantFiled: December 5, 2018Date of Patent: April 21, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Hardwell Chibvongodze
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Patent number: 10622367Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, and bit lines overlying the memory stack structures. Vertical discharge transistors are provided, each of which includes a respective vertical discharge transistor channel that extends through a second alternating stack of second insulating layers and second electrically conductive layers laterally spaced from the first alternating stack.Type: GrantFiled: September 26, 2018Date of Patent: April 14, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Masatoshi Nishikawa, Hardwell Chibvongodze
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Publication number: 20200098771Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, and bit lines overlying the memory stack structures. Vertical discharge transistors are provided, each of which includes a respective vertical discharge transistor channel that extends through a second alternating stack of second insulating layers and second electrically conductive layers laterally spaced from the first alternating stack.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Inventors: Masatoshi NISHIKAWA, Hardwell CHIBVONGODZE
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Patent number: 7974124Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. To control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.Type: GrantFiled: June 24, 2009Date of Patent: July 5, 2011Assignee: SanDisk CorporationInventors: Hardwell Chibvongodze, Manabu Sakai, Teruhiko Kamei
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Publication number: 20100329007Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. to control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.Type: ApplicationFiled: June 24, 2009Publication date: December 30, 2010Inventors: Hardwell Chibvongodze, Manabu Sakai, Teruhiko Kamei