Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.

Abstract: A semiconductor memory device including a channel region and a ferromagnetic gate is provided. The channel region can be formed within a semiconductor nanowire. The ferromagnetic gate is programmed with a selected orientation of magnetization by the electrical current that passes through the channel region in one direction or another. The orientation of the magnetization in the ferromagnetic gate can be detected by changes in the threshold voltage of a field effect transistor employing the ferromagnetic gate as a gate electrode, or can be detected by the resistance of the channel region that changes with the orientation of the magnetization in a two terminal device.

Abstract: Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and drain regions is formed employing a disposable gate spacer. The disposable gate spacer is removed to form a spacer cavity, which is filled with an anisotropic dielectric material to form an anisotropic gate spacer. The anisotropic dielectric material is aligned with an electrical field such that lengthwise directions of the molecules of the anisotropic dielectric material are aligned vertically within the spacer cavity. The anisotropic gate spacer provides a higher dielectric constant along the vertical direction and a lower dielectric constant along the horizontal direction.

Abstract: Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and drain regions is formed employing a disposable gate spacer. The disposable gate spacer is removed to form a spacer cavity, which is filled with an anisotropic dielectric material to form an anisotropic gate spacer. The anisotropic dielectric material is aligned with an electrical field such that lengthwise directions of the molecules of the anisotropic dielectric material are aligned vertically within the spacer cavity. The anisotropic gate spacer provides a higher dielectric constant along the vertical direction and a lower dielectric constant along the horizontal direction.

Abstract: According to an embodiment of the present invention is to provide methods to evaluate the impact of scrapped wafers on the remaining wafers in a lot by using scrap codes and statistical models. An embodiment of the present invention provides a method to obtain a baseline lot population by using cluster analysis model and functional limited yields. The functional limited yields may be for example chain limited yield, dc limited yield, or ac abist limited yield. By utilizing statistical modeling it is possible to determine which failures have an impact on the lot yield and require rework for the lot. In addition by monitoring the impact of failures, it is possible to determine if corrective actions need to be taken for lots that passed through a process prior to correction of the fault.