Patents by Inventor Harianto Wong
Harianto Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190067562Abstract: Methods and apparatus for a signal isolator having a dielectric interposer supporting first and second die each having a magnetic field sensing element. A first signal path extends from the first die to the second die and a second signal path extends from the second die to the first die. In embodiments, the first signal path is located in the interposer and includes a first coil to generate a magnetic field and the second signal path is located in the interposer and includes a second coil to generate a magnetic filed. The first coil is located in relation to the second magnetic field sensing element of the second die and the second coil is located in relation to the first magnetic field sensing element of the first die.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Applicant: Allegro MicroSystems, LLCInventors: Sundar Chetlur, Harianto Wong, Maxim Klebanov, William P. Taylor, Michael C. Doogue
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Patent number: 10162020Abstract: In one aspect, a Hall Effect sensing element includes a Hall plate having a thickness less than about 100 nanometers an adhesion layer directly in contact with the Hall plate and having a thickness in a range about 0.1 nanometers to 5 nanometers. In another aspect, a sensor includes a Hall Effect sensing element. The Hall Effect sensing element includes a substrate that includes one of a semiconductor material or an insulator material, an insulation layer in direct contact with the substrate, an adhesion layer having a thickness in a range of about 0.1 nanometers to 5 nanometers and in direct contact with the insulation layer and a Hall plate in direct contact with the adhesion layer and having a thickness less than about 100 nanometers.Type: GrantFiled: November 16, 2017Date of Patent: December 25, 2018Assignee: Allegro MicroSystems, LLCInventors: William P. Taylor, Harianto Wong
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Publication number: 20180149677Abstract: Systems and methods described herein are directed towards integrating a shield layer into a current sensor to shield a magnetic field sensing element and associated circuitry in the current sensor from electrical, voltage, or electrical transient noise. In an embodiment, a shield layer may be disposed along at least one surface of a die supporting a magnetic field sensing element. The shield layer may be disposed in various arrangements to shunt noise caused by a parasitic coupling between the magnetic field sensing element and the current carrying conductor away from the magnetic field sensing element.Type: ApplicationFiled: November 29, 2016Publication date: May 31, 2018Applicant: Allegro MicroSystems, LLCInventors: Shaun D. Milano, Bryan Cadugan, Michael C. Doogue, Alexander Latham, William P. Taylor, Harianto Wong, Sundar Chetlur
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Publication number: 20180074137Abstract: In one aspect, a Hall Effect sensing element includes a Hall plate having a thickness less than about 100 nanometers an adhesion layer directly in contact with the Hall plate and having a thickness in a range about 0.1 nanometers to 5 nanometers. In another aspect, a sensor includes a Hall Effect sensing element. The Hall Effect sensing element includes a substrate that includes one of a semiconductor material or an insulator material, an insulation layer in direct contact with the substrate, an adhesion layer having a thickness in a range of about 0.1 nanometers to 5 nanometers and in direct contact with the insulation layer and a Hall plate in direct contact with the adhesion layer and having a thickness less than about 100 nanometers.Type: ApplicationFiled: November 16, 2017Publication date: March 15, 2018Applicant: Allegro MicroSystems, LLCInventors: William P. Taylor, Harianto Wong
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Publication number: 20180033955Abstract: The present disclosure is directed towards a method for patterning a magnetic sensing layer. The method includes disposing a protective layer on a first of a substrate, disposing a first insulating layer on a first surface of protective layer. An opening is formed in the first insulating layer to expose the first surface of the protective layer. A magnetic sensing layer is disposed over the first insulating layer and a predetermined portion of the first surface of the protective layer within the opening. A second insulating layer can be disposed over the magnetic sensing layer. The second insulation layer and the magnetic sensing layer can be removed from the first insulation layer. Thus, the opening includes the magnetic sensing layer and the second insulation layer after the removal of the second insulation layer and magnetic sensing layer from the first insulation layer.Type: ApplicationFiled: July 26, 2016Publication date: February 1, 2018Applicant: Allegro MicroSystems, LLCInventors: Harianto Wong, William P. Taylor
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Patent number: 9865807Abstract: In one aspect, a method includes processing a metal substrate, performing a first etch on a first surface of the metal substrate to form, for an integrated circuit package, secondary leads and a curved component having two primary leads and performing a second etch, on a second surface of the substrate opposite the first surface, at locations on the secondary leads and locations on the curved component to provide a locking mechanism. Each primary lead located at a respective end of the curved component.Type: GrantFiled: October 7, 2015Date of Patent: January 9, 2018Assignee: Allegro MicroSystems, LLCInventors: Shixi Louis Liu, Harianto Wong, Paul A. David, John B. Sauber, Shaun D. Milano, Raguvir Kanda, Bruce Hemenway
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Patent number: 9857437Abstract: In one aspect, a Hall Effect sensing element includes a Hall plate having a thickness less than about 100 nanometers an adhesion layer directly in contact with the Hall plate and having a thickness in a range about 0.1 nanometers to 5 nanometers. In another aspect, a sensor includes a Hall Effect sensing element. The Hall Effect sensing element includes a substrate that includes one of a semiconductor material or an insulator material, an insulation layer in direct contact with the substrate, an adhesion layer having a thickness in a range of about 0.1 nanometers to 5 nanometers and in direct contact with the insulation layer and a Hall plate in direct contact with the adhesion layer and having a thickness less than about 100 nanometers.Type: GrantFiled: April 1, 2016Date of Patent: January 2, 2018Assignee: Allegro Microsystems, LLCInventors: William P. Taylor, Harianto Wong
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Publication number: 20160299200Abstract: In one aspect, a Hall Effect sensing element includes a Hall plate having a thickness less than about 100 nanometers an adhesion layer directly in contact with the Hall plate and having a thickness in a range about 0.1 nanometers to 5 nanometers. In another aspect, a sensor includes a Hall Effect sensing element. The Hall Effect sensing element includes a substrate that includes one of a semiconductor material or an insulator material, an insulation layer in direct contact with the substrate, an adhesion layer having a thickness in a range of about 0.1 nanometers to 5 nanometers and in direct contact with the insulation layer and a Hall plate in direct contact with the adhesion layer and having a thickness less than about 100 nanometers.Type: ApplicationFiled: April 1, 2016Publication date: October 13, 2016Applicant: Allegro Microsystems, LLCInventors: William P. Taylor, Harianto Wong
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Patent number: 9318481Abstract: In one aspect, a silicon-controller rectifier (SCR) includes a first N+ region; a first P+ region; a second N+ region; a second P+ region; and a P+/Intrinsic/N+ (PIN) diode disposed between the first P+ region and the second N+ region. The PIN diode includes a third N+ region, a third P+ region and an intrinsic material disposed between the third N+ region and the third P+ region. An anode terminal of the SCR connects to the first N+ region and the first P+ region and a cathode terminal of the SCR connects to the second N+ region and the second P+ region. A first distance between the third N+ region and the third P+ region controls the trigger voltage of the SCR and a second distance corresponding to a length of each of the third P+ region and the third N+ region controls the holding voltage of the SCR.Type: GrantFiled: September 8, 2015Date of Patent: April 19, 2016Assignee: Allegro Microsystems, LLCInventors: Zhixin Wang, Juin Jei Liou, Wei Liang, Richard B. Cooper, Maxim Klebanov, Harianto Wong
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Publication number: 20160028001Abstract: In one aspect, a method includes processing a metal substrate, performing a first etch on a first surface of the metal substrate to form, for an integrated circuit package, secondary leads and a curved component having two primary leads and performing a second etch, on a second surface of the substrate opposite the first surface, at locations on the secondary leads and locations on the curved component to provide a locking mechanism. Each primary lead located at a respective end of the curved component.Type: ApplicationFiled: October 7, 2015Publication date: January 28, 2016Inventors: Shixi Louis Liu, Harianto Wong, Paul A. David, John B. Sauber, Shaun D. Milano, Raguvir Kanda, Bruce Hemenway
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Patent number: 9190606Abstract: In one aspect, a method includes processing a metal substrate, performing a first etch on a first surface of the metal substrate to form, for an integrated circuit package, secondary leads and a curved component having two primary leads and performing a second etch, on a second surface of the substrate opposite the first surface, at locations on the secondary leads and locations on the curved component to provide a locking mechanism. Each primary lead located at a respective end of the curved component.Type: GrantFiled: March 15, 2013Date of Patent: November 17, 2015Assignee: Allegro Micosystems, LLCInventors: Shixi Louis Liu, Harianto Wong, Paul David, John B. Sauber, Shaun D. Milano, Raguvir Kanda, Bruce Hemenway
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Patent number: 9136060Abstract: A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be omitted and the second electrode may be in electrical contact with the substrate or may be formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor is provided by a pair of oppositely-directed diodes formed in the substrate connected in parallel with the capacitor. Capacitance is increased while maintaining a low effective series resistance. Electrodes include a plurality of fingers, which are interdigitated with the fingers of other electrode. The capacitor is fabricated in a wafer-scale process with other capacitors, where capacitors are separated from each other by a dicing technique.Type: GrantFiled: December 28, 2007Date of Patent: September 15, 2015Assignee: VISHAY-SILICONIXInventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
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Publication number: 20150061069Abstract: In one aspect, an integrated circuit (IC) includes an isolation trench dividing the IC into a first section and a second section, an active electronic device disposed in the first section of the IC and a capacitor disposed in the second section of the IC and electrically isolated from the active electronic device.Type: ApplicationFiled: September 5, 2013Publication date: March 5, 2015Applicant: Allegro Microsystems, LLCInventors: Andreas P. Friedrich, Harianto Wong
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Publication number: 20140264678Abstract: In one aspect, a method includes processing a metal substrate, performing a first etch on a first surface of the metal substrate to form, for an integrated circuit package, secondary leads and a curved component having two primary leads and performing a second etch, on a second surface of the substrate opposite the first surface, at locations on the secondary leads and locations on the curved component to provide a locking mechanism. Each primary lead located at a respective end of the curved component.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: Allegro Microsystems, Inc.Inventors: SHIXI LOUIS LIU, Harianto Wong, Paul David, John B. Sauber, Shaun D. Milano, Raguvir Kanda, Bruce Hemenway
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Patent number: 8384183Abstract: An integrated circuit and a method of making the integrated circuit provide a Hall effect element having a germanium Hall plate. The germanium Hall plate provides an increased electron mobility compared with silicon, and therefore, a more sensitive Hall effect element.Type: GrantFiled: February 19, 2010Date of Patent: February 26, 2013Assignee: Allegro Microsystems, Inc.Inventors: Harianto Wong, William P. Taylor, Ravi Vig
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Patent number: 8324711Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.Type: GrantFiled: March 30, 2011Date of Patent: December 4, 2012Assignee: Vishay Intertechnology, Inc.Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
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Publication number: 20110204460Abstract: An integrated circuit and a method of making the integrated circuit provide a Hall effect element having a germanium Hall plate. The germanium Hall plate provides an increased electron mobility compared with silicon, and therefore, a more sensitive Hall effect element.Type: ApplicationFiled: February 19, 2010Publication date: August 25, 2011Applicant: Allegro Microsystems, Inc.Inventors: Harianto Wong, William P. Taylor, Ravi Vig
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Patent number: 8004063Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.Type: GrantFiled: November 16, 2006Date of Patent: August 23, 2011Assignee: Vishay Intertechnology, Inc.Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
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Publication number: 20110176247Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.Type: ApplicationFiled: March 30, 2011Publication date: July 21, 2011Applicant: VISHAY INTERTECHNOLOGY, INC.Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
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Patent number: D719115Type: GrantFiled: March 15, 2013Date of Patent: December 9, 2014Assignee: Allegro Microsystems, LLCInventors: Shixi Louis Liu, Harianto Wong, Paul David, John B. Sauber, Shaun D. Milano, Raguvir Kanda, Bruce Hemenway