Abstract: A controller includes a buck gate driver coupled to first high-side switch and first low-side switch of a buck-boost (BB) converter. A zero crossing detection (ZCD) comparator is coupled to first low-side switch. The ZCD comparator is to, while the BB converter operates in buck mode: detect zero current flow through inductor; and turn off first low-side switch in response to detecting the zero current. A boost gate driver is coupled to second high-side switch and second low-side switch of the BB converter. A reverse current detection (RCD) comparator coupled to second high-side switch. The RCD comparator is to, while the BB converter operates in boost mode: detect zero current flow through second high-side switch; and turn off second high-side switch in response to detecting the zero current.

Abstract: A method comprising controlling operation, by a secondary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, a low-side field-effect transistor (FET). In response to controlling operation of the low-side FET, the method further includes triggering a zero-cross detection circuit. The method further includes measuring a first period of time between controlling operation of the low-side FET and triggering the zero-cross detection circuit. The method further includes measuring a second period of time between controlling operation of a high-side FET and triggering the zero-cross detection circuit. The method further includes adjusting a third period of time based on the first period of time and the second period of time, wherein the third period of time corresponds to a dead time between controlling operation of the high-side FET and the low-side FET.

Abstract: A secondary side controller for a flyback converter includes an integrated circuit (IC), which in turn includes: a synchronous rectifier (SR) sense pin coupled to a drain of an SR transistor on a secondary side of the flyback converter; a capacitor having a first side coupled to the SR sense pin, the capacitor to charge or discharge responsive to a voltage sensed at the SR sense pin; a diode-connected transistor coupled between a second side of the capacitor and ground; a first current mirror coupled to the diode-connected transistor and configured to receive, as input current, a reference current from a variable current source; and a peak detect transistor coupled to the diode-connected transistor and to an output of the first current mirror. The peak detect transistor is to output a peak detection signal in response to detecting current from the capacitor drop below the reference current.

Abstract: A system includes a first USB Type-C Power Delivery (USB-C/PD) port and a control circuit operatively coupled to the first USB-C/PD port. The control circuit is configured to determine whether a short circuit condition has occurred based on a first threshold voltage. The control circuit is also configured to turn off a ground isolation switch when short circuit condition occurs. The control circuit is further configured to determine a whether a voltage on a ground line is less than a second threshold voltage. The control circuit is further configured to turn on the ground isolation switch when the voltage on the ground line is less than the second threshold voltage. The control circuit may perform one or more error recovery operations after turning on the ground isolation switch.

Abstract: Controlling power factor correction (PFC) in a secondary-controlled alternating current (AC) to direct current (DC) (AC-DC) power adapter is described. In one embodiment, an apparatus includes a transformer, a primary-side controller coupled to the transformer, a PFC component coupled to the primary-side controller, and a secondary-side controller coupled to the transformer. The secondary-side controller is configured at least to obtain data informative of an amount of power, and control, based on the amount of power, a PFC operating mode of the PFC component.

Abstract: A primary-side-controlled fly-back converter is provided to eliminate cross-conduction between a power-switch (PS) on a primary side and a synchronous-rectifier (SR) on a secondary side when operating in continuous conduction mode (CCM). Generally, the converter includes a transformer having a primary coupled to a rectified AC input through the PS, and a secondary coupled to a DC output through the SR, the SR having a drain coupled to the secondary winding. A fly-back-controller includes a primary-controller operable to control a duty cycle of the PS, and a secondary-controller operable to turn OFF the SR when the PS turns ON in CCM. The secondary-controller includes a CCM zero-crossing-detector comparator having a first input coupled to the drain of the SR through a capacitor, and is operable to detect a sharp change in a drain voltage when the PS turns ON during CCM, and to output a signal to turn OFF the SR.

Abstract: Controlling an active clamp field effect transistor (FET) and a primary-side FET in a secondary-controlled active clamp converter is described. In one embodiment, an apparatus includes a primary-side FET coupled to a transformer and an active clamp FET disposed on a primary side of the transformer. A secondary-side controller is configured to control the active clamp FET and the primary-side FET across a same galvanic isolation barrier.

Abstract: A controller includes a buck gate driver coupled to first high-side switch and first low-side switch of a buck-boost (BB) converter. A zero crossing detection (ZCD) comparator is coupled to first low-side switch. The ZCD comparator is to, while the BB converter operates in buck mode: detect zero current flow through inductor; and turn off first low-side switch in response to detecting the zero current. A boost gate driver is coupled to second high-side switch and second low-side switch of the BB converter. A reverse current detection (RCD) comparator coupled to second high-side switch. The RCD comparator is to, while the BB converter operates in boost mode: detect zero current flow through second high-side switch; and turn off second high-side switch in response to detecting the zero current.

Abstract: A secondary side controller for a flyback converter can include a synchronous rectifier (SR) gate driver pin coupled to a gate of an SR transistor on a secondary side of the flyback converter. An error amplifier is coupled to an output of a voltage bus of the flyback converter, the error amplifier to generate an error signal indicative of a voltage of the output of the voltage bus. Control logic is coupled to the error amplifier and to the SR transistor, the control logic to: detect when the voltage is at least a threshold percentage higher than a sink voltage required by a sink device coupled to the output of the voltage bus; detect assertion of a skip mode signal; and cause the SR transistor to be driven during a skip mode such as to partially discharge an output capacitor coupled to the output of the voltage bus.

Abstract: A system includes a first USB Type-C Power Delivery (USB-C/PD) port and a control circuit operatively coupled to the first USB-C/PD port. The control circuit is configured to determine whether a short circuit condition has occurred based on a first threshold voltage. The control circuit is also configured to turn off a ground isolation switch when short circuit condition occurs. The control circuit is further configured to determine a whether a voltage on a ground line is less than a second threshold voltage. The control circuit is further configured to turn on the ground isolation switch when the voltage on the ground line is less than the second threshold voltage. The control circuit may perform one or more error recovery operations after turning on the ground isolation switch.

Abstract: Universal Serial Bus Type-C (USB-C) controllers with a floating gate driver with programmable drive strength for a wide range of USB power delivery applications in electronic devices described. A USB-C controller includes a floating gate driver and control logic. The floating gate driver includes p-channel field-effect transistors (FETs) coupled in parallel between a first terminal and a second terminal and p-channel pre-gate drivers. Each p-channel pre-gate driver is coupled to a gate of one of the p-channel FETs. The floating gate driver includes n-channel FETs coupled in parallel between the second terminal and a third terminal and n-channel pre-gate drivers, each n-channel pre-gate driver being coupled to a gate of one of the plurality of n-channel FETs. The control logic sends one or more control signals to activate a first number of p-channel pre-gate drivers and a second number of n-channel pre-gate drivers based on an output voltage.

Abstract: A mode-transition architecture for USB controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes a controller coupled to a slope compensation circuit, the controller to detect a transition of a buck-boost converter from a first mode having a first duty cycle to a second mode having a second duty cycle that is less or more than the first duty cycle. The controller controls the slope compensation circuit to nullify an error in an output caused by the transition. The controller can cause the slope compensation circuit to apply a charge stored in a capacitor during a first cycle to start a second cycle with a higher voltage than the first cycle.

Abstract: Communicating fault conditions between primary-side and secondary-side controllers of a Universal Serial Bus Power Delivery (USB-PD) device is described. The primary-side controller receives a control signal from the secondary-side controller across a galvanic isolation barrier. The primary-side controller converts the control signal into a first pulse signal and applies the first pulse signal to control a primary-side switch. When the primary-side controller detects that a first fault condition has occurred, the primary-side controller communicates a first information signal about the first fault condition to the secondary-side controller across the galvanic isolation barrier. The first information signal is generated by converting the control signal into a second pulse signal having a different pulse width than the first pulse signal. The primary-side controller applies the second pulse signal to control the primary-side power switch.

Abstract: A secondary side controller for a flyback converter includes an integrated circuit (IC), which in turn includes: a synchronous rectifier (SR) sense pin coupled to a drain of an SR transistor on a secondary side of the flyback converter; a capacitor having a first side coupled to the SR sense pin, the capacitor to charge or discharge responsive to a voltage sensed at the SR sense pin; a diode-connected transistor coupled between a second side of the capacitor and ground; a first current mirror coupled to the diode-connected transistor and configured to receive, as input current, a reference current from a variable current source; and a peak detect transistor coupled to the diode-connected transistor and to an output of the first current mirror. The peak detect transistor is to output a peak detection signal in response to detecting current from the capacitor drop below the reference current.

Abstract: A secondary-side-controller for a QR flyback converter and method for operating the same are provided. Generally, the secondary-side-controller includes a driver configured to control a power-switch (PS) on a primary side of converter to turn on the PS when a sinusoidal input voltage to the converter is at one of a plurality of valleys, an analog-to-digital-converter (ADC) to read the input voltage, output voltage, and load current, and generate digital signals based thereon. A valley-controller coupled to the driver, ADC, a look-up-table and a pulse width modulator (PWM) receives the signals from the ADC and using the look-up-table determines at which valley of the plurality of valleys to couple a PWM signal from the PWM to the driver. The valley-controller is operable for each switching cycle of the PS to increment, decrement or leave unchanged the valley at which the PWM signal is coupled from the PWM to the driver.

Abstract: An IC controller for USB Type-C device includes an error amplifier (EA), which includes an EA output coupled to a PWM comparator of a buck-boost converter; a first transconductance amplifier to adjust a current at the EA output, the first transconductance amplifier operating in a constant voltage mode; and a second transconductance amplifier to adjust the current at the EA output, the second transconductance amplifier operating in a constant current mode. A first set of programmable registers is to store a first set of increasingly higher transconductance values. A second set of programmable registers is to store a second set of increasingly higher transconductance values. Control logic is to: cause the first transconductance amplifier to operate while sequentially using transconductance values stored in the first set of programmable registers; and cause the second transconductance amplifier to operate while sequentially using transconductance values stored in the second set of programmable registers.

Abstract: A mode-transition architecture for USB controllers is described herein. In an example embodiment, an integrated circuit (IC) controller includes a controller coupled to a slope compensation circuit, the controller to detect a transition of a buck-boost converter from a first mode having a first duty cycle to a second mode having a second duty cycle that is less or more than the first duty cycle. The controller controls the slope compensation circuit to nullify an error in an output caused by the transition. The controller can cause the slope compensation circuit to apply a charge stored in a capacitor during a first cycle to start a second cycle with a higher voltage than the first cycle.

Abstract: An IC controller for a USB Type-C device includes a register that is programmable to store a pulse width and a frequency. A buck-boost converter of the controller includes a first high-side switch and a second high-side switch. Control logic is coupled to the register and gates of the first/second high-side switches. To perform a soft start in one of buck mode or boost mode, the control logic: causes the second high-side switch to operate in diode mode; retrieves values of the pulse width and the frequency from the register; causes the first high-side switch to turn on using pulses having the pulse width and at the frequency; detects an output voltage at the output terminal of the buck-boost converter that exceeds a threshold value; and in response to the detection, transfers control of the buck-boost converter to an error amplifier loop coupled to the control logic.

Abstract: A multi-port USB Type-C® Power Delivery (USB-C/PD) power converter for switching clock phase shifts is described herein. The multi-port USB-C/PD power converter includes a first PD port, a second PD port, and a power controller coupled to the first and second PD ports. The power controller includes a first phased clock generator to generate a first phase-shifted clock signal by shifting a clock signal by a first phase with respect to a reference clock signal, and a second phased clock generator to generate a second phase-shifted clock signal to generate a second phased-shifted clock signal by shifting the clock signal by a second phase with respect to the reference clock signal. The first PD port and the second PD port output power in response to a first control signal based on the first phase-shifted clock signal and a second control signal based on the second phase-shifted clock signal, respectively.

Abstract: A multi-port Universal Serial Bus Type-C (USB-C) controller with ground and supply cable compensation technologies is described. A USB-C controller includes a first power control circuit (PCU) coupled to a system ground terminal and a first ground terminal and a second PCU coupled to the system ground terminal and a second ground terminal. The first PCU receives a first ground signal indicative of a first ground potential at a first USB-C connector and adjusts a first power voltage line (VBUS) signal on the first VBUS terminal based on the first ground signal and the system ground. The second PCU receives a second ground signal indicative of a second ground potential at a second USB-C connector and adjusts a second VBUS signal on the second VBUS terminal based on the second ground signal and the system ground.