Abstract: A secondary-side controller for an AC-DC converter that has a single synchronous rectifier sensing (SR_SNS) terminal, coupled to a synchronous rectifier (SR) of the AC-DC converter, and a voltage divider circuit coupled to the single SR_SNS terminal configured to provide signals to a sensing circuit. The voltage divider includes an active diode, an internal resistive element, and a switch, in which the active diode is configured to control the switch to enable or disable the internal resistive element based on a comparison result of a voltage at the single SR_SNS terminal and a reference voltage.

Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. In an example embodiment, an integrated circuit (IC) controller for the secondary side of the AC-DC converter comprises a zero-crossing detector (ZCD) block and a negative-sensing (NSN) block coupled to a terminal. The terminal is configured to receive an input signal from a drain node of a SR circuit on the secondary side of the AC-DC converter. The ZCD block is configured to determine when a voltage of the input signal reaches 0V. The NSN block is configured to determine a negative voltage of the input signal. An internal rectifier, coupled between the terminal and local ground, is configured to ensure that substantially no current flows through the terminal during operation of the ZCD block and the NSN block.

Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. In an example embodiment, an integrated circuit (IC) controller for the secondary side of the AC-DC converter comprises a zero-crossing detector (ZCD) block and a negative-sensing (NSN) block coupled to a terminal. The terminal is configured to receive an input signal from a drain node of a SR circuit on the secondary side of the AC-DC converter. The ZCD block is configured to determine when a voltage of the input signal reaches 0V. The NSN block is configured to determine a negative voltage of the input signal. An internal rectifier, coupled between the terminal and local ground, is configured to ensure that substantially no current flows through the terminal during operation of the ZCD block and the NSN block.

Abstract: Communicating fault indications between primary and secondary controller in a secondary-controlled flyback converter is described. In one embodiment, an apparatus includes a primary-side field effect transistor (FET) coupled to a flyback transformer coupled to the primary-side FET, and a primary-side controller coupled to the flyback transformer. The primary-side controller is configured to receive a signal from a secondary-side controller across a galvanic isolation barrier, apply a pulse signal to the primary-side FET in response to the signal to turn-on and turn-off the primary-side FET, communicate information to the secondary-side controller across the flyback transformer by varying a first pulse width of the pulse signal to a second pulse width and applying the pulse signal with the second pulse width to the primary-side FET.

Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side IC controller of the AC-DC converter includes a SR-SNS pin coupled to a peak-detector block, a zero-crossing block, and a calibration block. The calibration block is configured to: measure a loop turn-around delay (Tloop), a time (Tpkpk) between two successive peak voltages detected on the SR-SNS pin, and a time (Tzpk) from when the voltage sensed on the SR-SNS pin crosses zero voltage to when a peak voltage is detected on the SR-SNS pin; and set timing for a signal to turn on a power switch in a primary side of the AC-DC converter based at least on Tloop, Tpkpk, and Tzpk.

Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC controller of the AC-DC converter includes a peak-detector block coupled to detect peak voltages sensed on a SR-SNS pin. The peak-detector block comprises a peak comparator, a sample-and-hold (S/H) circuit, and a DC offset circuit. The peak comparator is coupled to receive a sinusoidal input from the SR-SNS pin. The S/H circuit is coupled to sample the sinusoidal input and to provide a peak sampled voltage. The DC offset voltage circuit is coupled between the output of the S/H circuit and a reference voltage input of the peak comparator to subtract a DC offset voltage from the peak sampled voltage.

Abstract: Communicating information stored at a secondary controller to a primary controller in a secondary-controlled flyback converter is described. In one embodiment, a method includes storing, by a secondary-side controller of a power converter, calibration information associated with a primary-side controller of the power converter. The power converter is a secondary-controlled alternating current to direct current (AC-DC) flyback converter comprising a galvanic isolation barrier. The method further includes sending, by the secondary-side controller, the calibration information to the primary-side controller across the galvanic isolation barrier in response to power-up of the power converter.

Abstract: An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC) controller of the AC-DC converter includes a SR-SNS pin, a VBUS_IN pin, a first voltage-to-current converter, a sample-and-hold (S/H) circuit, a second voltage-to-current converter, and a signal generation circuit. The first voltage-to-current converter is coupled to remove a component of the output bus voltage sensed on the VBUS_IN pin from the voltage sensed on the SR-SNS pin. The S/H circuit is coupled to sample the voltage sensed on the SR-SNS pin and to provide a sampled voltage. The second voltage-to-current converter is coupled to convert the sampled voltage to a feed-forward current. The signal generation circuit is coupled to receive the feed-forward current and to generate feed-forward signals used to control operation of a primary side of the AC-DC converter.

Abstract: Communicating information stored at a secondary controller to a primary controller in a secondary-controlled flyback converter is described. In one embodiment, a method includes storing, by a secondary-side controller of a power converter, calibration information associated with a primary-side controller of the power converter. The power converter is a secondary-controlled alternating current to direct current (AC-DC) flyback converter comprising a galvanic isolation barrier. The method further includes sending, by the secondary-side controller, the calibration information to the primary-side controller across the galvanic isolation barrier in response to power-up of the power converter.

Abstract: Communicating information stored at a secondary controller to a primary controller in a secondary-controlled flyback converter is described. In one embodiment, a method includes storing, by a secondary-side controller of a power converter, calibration information associated with a primary-side controller of the power converter. The power converter is a secondary-controlled alternating current to direct current (AC-DC) flyback converter comprising a galvanic isolation barrier. The method further includes sending, by the secondary-side controller, the calibration information to the primary-side controller across the galvanic isolation barrier in response to power-up of the power converter.

Abstract: Communicating information stored at a secondary controller to a primary controller in a secondary-controlled flyback converter is described. In one embodiment, a method includes storing, by a secondary-side controller of a power converter, calibration information associated with a primary-side controller of the power converter. The power converter is a secondary-controlled alternating current to direct current (AC-DC) flyback converter comprising a galvanic isolation barrier. The method further includes sending, by the secondary-side controller, the calibration information to the primary-side controller across the galvanic isolation barrier in response to power-up of the power converter.

Abstract: A secondary side controller for an AC-DC converter and method for operating the same are provided. Generally, the controller includes a single synchronous rectifier sense (SR-SNS) pin coupled to a drain of a SR on a secondary of a transformer to sense a voltage (VSRD). In feed-forward (FF) mode VSRD is a sum of a voltage (VIN) on a primary divided by a turn-ratio (N) of the transformer and an output bus voltage (VBUS). A voltage-to-current (V2I) converter coupled to the SR-SNS pin and to the output bus removes VBUS from VSRD. A sample and hold (S/H) module coupled to the SR-SNS pin samples a voltage (VSAMP) including information on VIN/N. A VIN/N V2I converter coupled to the S/H module converts VSAMP to a feed-forward current (IFF), and a cancellation and signal module coupled thereto extracts information on VIN from IFF and generates signals to control the AC-DC converter.

Abstract: An AC-DC converter with secondary side controller and synchronous rectifier (SR) architecture and method for operating the same are provided. Generally, the controller is implemented as an integrated circuit including a peak-detector module having a peak comparator with a first input coupled to a drain of the SR through a single SR sense (SR-SNS) pin to receive a sinusoidal input. A sample and hold (S/H) circuit with an input coupled to the SR-SNS pin samples the sinusoidal input and holds on an output of thereof a peak sampled voltage received on the input. A direct current (DC) offset voltage coupled between the output of the S/H circuit and the second input of the peak comparator subtracts an DC offset voltage from the peak sampled voltage to compensate for DC offset inaccuracies introduced by the S/H circuit and the peak comparator. Other embodiments are also disclosed.

Abstract: A flyback converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided. Generally, the secondary side controller includes an integrated circuit (IC) including a single SR-SNS pin coupled to a drain of a SR on a secondary side of the converter to sense a voltage on the drain, and a power switch (PS) drive pin coupled to a PS on a primary side to turn on the PS in response to a number of measurements based on the voltage sensed on the drain of the SR. The IC includes a calibration block to measure a loop turn-around delay, valley delays with respect to zero-crossing and set timing for a signal to turn on the PS in response to the voltage sensed on the drain of the SR at or very close the primary side valley improving efficiency and performance of the converter.

Abstract: An AC-DC converter with secondary side control and synchronous rectifier (SR) architecture and method for operating the same are provided for reducing the cost, complexity and size of the converter while improving efficiency. Generally, the secondary side controller includes a zero-crossing detector block, a negative-sensing block, a peak-detector block and a line-feed-forward block integrated in an integrated circuit (IC), and coupled to a secondary side of the converter through a single SR-sense (SR_SNS) pin through which the IC is coupled to a drain of the SR. The single SR_SNS pin has a maximum input voltage less than a rectified AC input voltage input to a secondary side of the converter, and, in one embodiment, is coupled to the drain of the SR through a voltage divider circuit including circuit elements both internal and external to the IC along with a rectifier element in series with the internal resistor.

Abstract: A circuit in accordance with one embodiment of the invention can include a light emitting diode (LED) assembly comprising a plurality of LED channels that are controlled independently with a switch mode driver. The circuit also includes N+1 wires coupled to said LED assembly, where N is equal to the number of said plurality of LED channels of said LED assembly.

Abstract: An adaptive algorithm running on a processing device receives a temperature value that represents a temperature at a gate terminal of a transistor. The adaptive algorithm, determines a drive strength value that represents a drive strength for a signal based on the temperature value. A signal with the determined drive strength is applied to the gate terminal of the transistor.

Abstract: An embodiment of the present invention is directed to a method and circuit to control light emitting diode (LED) output. The method includes receiving a line voltage signal which powers a lighting circuit comprising an LED and determining an adjustment of a threshold based on a variation of the line voltage signal and/or a controller delay or other practical controller limitation or imperfection. The method further includes dynamically adjusting a threshold or other reference of a controller which controls a switch of said lighting circuit for compensating for line variations to maintain a substantially uniform LED current.

Abstract: A circuit may include a switch mode power converter that intermittently enables a current path in response to a switch control signal; a duty cycle measurement circuit that generates a duty cycle value corresponding to a duty cycle of the switch control signal; and an evaluation circuit that activates a failure indication in response to the duty cycle value being outside of at least one limit.

Abstract: A light emitting driver circuit, system, and method are provided. The driver circuit system and method can be implemented in various ways. An embodiment includes a bypass circuit which diverts current from the LEDs whenever a switch coupled to the LEDs incurs residual current when turned off. In an additional or alternative embodiment, the residual current can be sensed and the amount of residual current used to trigger fetching of a compensation value. That compensation value can change a dimming function forwarded to the switch in order to compensate for, offset, or substantially eliminate the residual current through that switch.