Patents by Inventor Harish K. Krishnamurthy
Harish K. Krishnamurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230341444Abstract: Embodiments herein relate to a current sensor for a power converter such as a buck converter. The power converter is fabricated on a high bandgap semiconductor die while the current sensor includes a portion on the same die and a portion on a silicon die. The portion on the same die includes a sense transistor, while the portion on the silicon die includes a feedback circuit for controlling a voltage of the sense transistor to ensure it is biased according to the bias of a switching transistor of the power converter. A current of the sense transistor can then be processed such as by an averaging or sampling process.Type: ApplicationFiled: April 22, 2022Publication date: October 26, 2023Inventors: Nachiket Desai, Harish K. Krishnamurthy
-
Publication number: 20230205244Abstract: An apparatus, system, and method for digital voltage regulator (DVR) control are provided. A DVR includes comparators configured to determine whether VLOAD drops below a gradual non-linear control (NLC) undershoot threshold voltage, rises above or drops below a reference voltage, and rises above a gradual NLC overshoot threshold voltage, respectively, power gates (PGs) configured to adjust VOUT based on a provided PG code; and VR controller circuitry comprising synchronous LC circuitry configured to increase or decrease, by a first increment, the PG code responsive to the VLOAD dropping below the reference voltage and rising above the reference voltage, and asynchronous gradual NLC circuitry configured to increase or decrease, by a second increment greater than the first increment and less than half a maximum PG code value, the PG code responsive to the VLOAD dropping below the gradual NLC undershoot threshold voltage and rising above the gradual NLC overshoot threshold voltage.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: Anand Ramasundar, Cary Renzema, Fabrice Paillet, James Keith Hodgson, Po-Cheng Chen, Sergio Carlo Rodriguez, Harish K. Krishnamurthy, Jason Muhlestein
-
Publication number: 20230092022Abstract: An apparatus, system, and method for voltage regulator (VR) control are provided. An apparatus can include first, second, and third comparators configured to determine whether a load voltage (VLOAD) drops below a lower non-linear control (NLC) threshold, drops below a lower linear control (LC) threshold, and exceeds an upper LC threshold, respectively. The apparatus can include power gates (PGs) configured to adjust an output voltage (VOUT) based on a provided power gate (PG) code. The apparatus can include voltage regulator (VR) controller circuitry comprising synchronous LC circuitry and asynchronous NLC circuitry, the LC circuitry configured to increment or decrement the PG code responsive to the VLOAD dropping below the LC threshold and exceeding the upper LC threshold, respectively, and the NLC circuitry configured to increase the PG code based on a number of consecutive NLC droop events and responsive to the VLOAD dropping below the lower NLC threshold.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Fabrice Paillet, Anand Ramasundar, Khondker Ahmed, Harish K. Krishnamurthy, Cary Renzema, Christopher Mandic, James Keith Hodgson
-
Publication number: 20220374060Abstract: A computational current sensor, that enhances traditional Kalman filter based current observer techniques, with transient tracking enhancements and an online parasitic parameter identification that enhances overall accuracy during steady state and transient events while guaranteeing convergence. During transient operation (e.g., a voltage droop), a main filter is bypassed with estimated values calculated from a charge balance principle to enhance accuracy while tracking transient current surges of the DC-DC converter. To address the issue of dependency on a precise model parameter information and further improve accuracy, an online identification algorithm is included to track the equivalent parasitic resistance at run-time.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Applicant: Intel CorporationInventors: Harish K. Krishnamurthy, Xun Sun, Krishnan Ravichandran
-
Patent number: 10958079Abstract: In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.Type: GrantFiled: March 28, 2018Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Xiaosen Liu, Khondker Z. Ahmed, Vivek K. De, Nachiket V. Desai, Suhwan Kim, Harish K. Krishnamurthy, Turbo Majumder, Krishnan Ravichandran, Christopher Schaef, Vaibhav A. Vaidya, Sriram R. Vangal
-
Patent number: 10942556Abstract: Systems, apparatuses and methods may provide for early pre-charge with respect to peak power events. Application performance may improve by pre-charging a supercap just prior to initiating a system wake up from a qualified system wake-source trigger. Additionally, the pre-charging of the supercap may be controlled by a time defined pre-charge period and may also be controlled by a predetermined threshold voltage.Type: GrantFiled: August 22, 2017Date of Patent: March 9, 2021Assignee: Intel CorporationInventors: Dileep J. Kurian, Ankit Gupta, Akhila M, Tanay Karnik, Vaibhav Vaidya, David Arditti Ilitzky, Christopher Schaef, Sriram Kabisthalam Muthukumar, Harish K. Krishnamurthy, Suhwan Kim
-
Patent number: 10630078Abstract: Some embodiments include apparatus and methods for using a switch to couple an inductor to an energy harvester for a time interval to allow charging of the inductor during the time interval, and using a circuit to generate control information for power management. A value of the control information is based on a value of the time interval.Type: GrantFiled: March 25, 2016Date of Patent: April 21, 2020Assignee: Intel CorporationInventors: Sally Safwat Amin, Vaibhav Vaidya, Harish K. Krishnamurthy
-
Patent number: 10474174Abstract: An apparatus is provided which includes: a first set of devices which is digitally controlled by a first feedback loop that includes a first comparator; and a second set of devices which is controlled by an analog circuitry which is part of a second feedback loop that includes an amplifier, wherein the first set of devices is coupled in parallel to the second set of devices.Type: GrantFiled: April 4, 2017Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Taesik Na, Harish K. Krishnamurthy, Xiaosen Liu
-
Patent number: 10345881Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.Type: GrantFiled: July 19, 2017Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Ramnarayanan Muthukaruppan, Harish K. Krishnamurthy, Mohit Verma, Pradipta Patra, Uday Bhaskar Kadali
-
Publication number: 20190094931Abstract: Various embodiments of the invention may analyze previous patterns of harvested energy to predict future patterns of available harvested energy. This prediction may then be used to choose from among multiple methods of energy reduction techniques. The energy reduction techniques may include multiple versions of reducing or modifying instruction execution. Reduced instruction execution may include reducing the precision of various calculations.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Applicant: INTEL CORPORATIONInventors: Khondker Z. Ahmed, Vivek K. De, Nachiket V. Desai, Suhwan Kim, Harish K. Krishnamurthy, Xiaosen Liu, Turbo Majumder, Krishnan Ravichandran, Christopher Schaef, Vaibhav Vaidya, Sriram R. Vangal
-
Publication number: 20190064907Abstract: Systems, apparatuses and methods may provide for early pre-charge with respect to peak power events. Application performance may improve by pre-charging a supercap just prior to initiating a system wake up from a qualified system wake-source trigger. Additionally, the pre-charging of the supercap may be controlled by a time defined pre-charge period and may also be controlled by a predetermined threshold voltage.Type: ApplicationFiled: August 22, 2017Publication date: February 28, 2019Inventors: Dileep J. Kurian, Ankit Gupta, Akhila M, Tanay Karnik, Vaibhav Vaidya, David Arditti Ilitzky, Christopher Schaef, Sriram Kabisthalam Muthukumar, Harish K. Krishnamurthy, Suhwan Kim
-
Publication number: 20190044341Abstract: In one embodiment, an energy harvesting system includes multiple-input-multiple-output switched-capacitor (MIMOSC) circuitry comprising a plurality of switched-capacitor circuit units to receive a plurality of direct current (DC) input voltages at respective input terminals of the switched-capacitor circuit unit, combine the received DC input voltages, and provide the combined DC input voltages at an output terminal of the switched-capacitor circuit unit. The energy harvesting system also includes maximum power point tracking (MPPT) circuitry coupled to switches of the switched-capacitor circuit units of the MIMOSC circuitry. The MPPT circuitry is to provide a plurality of switching signals to the switches of the switched-capacitor circuit units. The MIMOSC circuitry is to provide a plurality of DC output voltages to respective loads based on the switching signals from the MPPT circuitry.Type: ApplicationFiled: March 28, 2018Publication date: February 7, 2019Inventors: Xiaosen Liu, Khondker Z. Ahmed, Vivek K. De, Nachiket V. Desai, Suhwan Kim, Harish K. Krishnamurthy, Turbo Majumder, Krishnan Ravichandran, Christopher Schaef, Vaibhav A. Vaidya, Sriram R. Vangal
-
Patent number: 10185382Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.Type: GrantFiled: October 12, 2016Date of Patent: January 22, 2019Assignee: Intel CorporationInventors: Ramnarayanan Muthukaruppan, Harish K. Krishnamurthy, Mohit Verma, Pradipta Patra, Uday Bhaskar Kadali
-
Publication number: 20180284823Abstract: An apparatus is provided which includes: a first set of devices which is digitally controlled by a first feedback loop that includes a first comparator; and a second set of devices which is controlled by an analog circuitry which is part of a second feedback loop that includes an amplifier, wherein the first set of devices is coupled in parallel to the second set of devices.Type: ApplicationFiled: April 4, 2017Publication date: October 4, 2018Applicant: INTEL CORPORATIONInventors: Taesik NA, Harish K. KRISHNAMURTHY, Xiaosen LIU
-
Patent number: 9948186Abstract: Described is an apparatus which comprises: a first bridge to be coupled to a first load; a first Pulse Width Modulation (PWM) circuit to drive the first bridge; a second bridge to be coupled to a second load; and a second PWM circuit to drive the second bridge, wherein the first PWM circuit is controlled by a first digital word separate from a second digital word, wherein the second PWM circuit is controlled by the second digital, and wherein the second digital word is derived from the first digital word.Type: GrantFiled: June 21, 2016Date of Patent: April 17, 2018Assignee: INTEL CORPORATIONInventors: Nicholas P. Cowley, Harish K. Krishnamurthy, Ruchir Saraswat
-
Patent number: 9882383Abstract: Examples may include a smart power delivery network using voltage regulators to supply combined power sufficient to meet a peak load demand generated from one load from among multiple possible loads. A system of power gate devices having controllers may assist in dynamically steering current driven by the voltage regulators to the multiple possible loads.Type: GrantFiled: December 23, 2014Date of Patent: January 30, 2018Assignee: INTEL CORPORATIONInventors: Harish K. Krishnamurthy, Khondker Z. Ahmed, Krishnan Ravichandran
-
Publication number: 20170315601Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Inventors: Ramnarayanan MUTHUKARUPPAN, Harish K. KRISHNAMURTHY, Mohit VERMA, Pradipta PATRA, Uday Bhaskar KADALI
-
Publication number: 20170279276Abstract: Some embodiments include apparatus and methods for using a switch to couple an inductor to an energy harvester for a time interval to allow charging of the inductor during the time interval, and using a circuit to generate control information for power management. A value of the control information is based on a value of the time interval.Type: ApplicationFiled: March 25, 2016Publication date: September 28, 2017Inventors: Sally Safwat Amin, Vaibhav Vaidya, Harish K. Krishnamurthy
-
Patent number: 9766678Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.Type: GrantFiled: February 4, 2013Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Ramnarayanan Muthukaruppan, Harish K. Krishnamurthy, Mohit Verma, Pradipta Patra, Uday Bhaskar Kadali
-
Patent number: 9710422Abstract: Methods and apparatus relating to low cost and/or low overhead serial interface for power management and other IC (Integrated Circuit) devices are described. In an embodiment, a unique address is assigned to each of a plurality of slave devices. The plurality of slave devices are coupled in a daisy chain configuration. And, any access directed at a first slave device from the plurality of slave devices is allowed based at least in part on comparison of an address of the first slave device and an address associated with the access. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 15, 2014Date of Patent: July 18, 2017Assignee: Intel CorporationInventors: Sheldon Weng, George E. Matthew, Pavan Kumar, Wayne L. Proefrock, Harish K. Krishnamurthy, Krishnan Ravichandran