Abstract: A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have values selected from a set of at least three entry values and 2n distinct inputs can be encoded into k-entry codewords for some n>k. A vector storage element comprising k cells can store an k electrical quantities (voltage, current, etc.) corresponding to a codeword. The voltage code is such that, for at least one position of a vector, there are at least three vectors having distinct entry values at that position and, for at least a subset of the possible codewords, the sum of the entry values over the positions of each vector is constant from vector to vector in that subset. The storage device might be an integrated circuit device, a discrete memory device, or a device having embedded memory.

Abstract: A memory circuit, such as an embedded DRAM array, stores information as groups of bits or data using information coding in storage and retrieval data, instead of each bit being stored separately. Write data words can be mapped to storage format words that are stored and defined by a Hadamard matrix. The storage format word is stored as charge levels in an addressable memory location. For retrieving stored data, charge levels are read from the storage cells and interpreted to a valid storage format word. Hadamard code maximal likelihood decoding can be used to derive a read data word corresponding to a previously written write data word. The write data word is then output as the result of a read of the selected addressable location, or a portion thereof. The mapping can be two or more Hadamard matrix mappings concatenated for each of a plurality of storage format words.

Abstract: A sorting decoder captures the rank-order of a set of input analogue signals in the digital domain using simple logic components such as self-timed first state elements, without requiring conventional analogue-to-digital signal converters. The analogue signals are each compared against a monotonic dynamic reference and the resulting comparisons are snapshot by a self-timed first state element for each input signal, or the last member of a sorted collection of input signals, at the time when it reaches the reference signal, so that a different snapshot representing the signal value ranking relative to the other signal values is produced for each input signal. The resulting rank-order estimation snapshots are binary signals that can then be further processed by a simple sorting logic circuit based on elementary logic components.

Abstract: Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. Hybrid transformers that apply such transformations to selected subsets of signals to be transmitted may be used to adapt to various signal set sizes and/or transmission environment properties including noise and physical space requirements of given transmission environments.

Abstract: A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have values selected from a set of at least three entry values and 2n distinct inputs can be encoded into k-entry codewords for some n>k. A vector storage element comprising k cells can store an k electrical quantities (voltage, current, etc.) corresponding to a codeword. The voltage code is such that, for at least one position of a vector, there are at least three vectors having distinct entry values at that position and, for at least a subset of the possible codewords, the sum of the entry values over the positions of the each vector is constant from vector to vector in that subset. The storage device might be an integrated circuit device, a discrete memory device, or a device having embedded memory.

Abstract: A memory circuit, such as an embedded DRAM array, stores information as groups of bits or data using information coding in storage and retrieval data, instead of each bit being stored separately. Write data words can be mapped to storage format words that are stored and defined by a Hadamard matrix. The storage format word is stored as charge levels in an addressable memory location. For retrieving stored data, charge levels are read from the storage cells and interpreted to a valid storage format word. Hadamard code maximal likelihood decoding can be used to derive a read data word corresponding to a previously written write data word. The write data word is then output as the result of a read of the selected addressable location, or a portion thereof. The mapping can be two or more Hadamard matrix mappings concatenated for each of a plurality of storage format words.

Abstract: A sorting decoder captures the rank-order of a set of input analogue signals in the digital domain using simple logic components such as self-timed first state elements, without requiring conventional analogue-to-digital signal converters. The analogue signals are each compared against a monotonic dynamic reference and the resulting comparisons are snapshot by a self-timed first state element for each input signal, or the last member of a sorted collection of input signals, at the time when it reaches the reference signal, so that a different snapshot representing the signal value ranking relative to the other signal values is produced for each input signal. The resulting rank-order estimation snapshots are binary signals that can then be further processed by a simple sorting logic circuit based on elementary logic components.

Abstract: Systems and methods for freeform additive manufacturing are disclosed. A system includes a positioning device configured to alter location during a manufacturing process of an object. The positioning device includes at least one nozzle configured to dispense a material to create the object. The material can include at least one position code. The positioning device further includes an image sensor configured to create an image of the object and a processor configured to identify the position code based on the image of the object and determine a position of the object based on the position code.

Abstract: Circuits that are matched to balanced codes may recover transmitted information in a noise resilient and power efficient manner. Circuit components for processing a balanced code may include one or more of: matched amplification of the signals representing the balanced code, matched equalization and/or filtering on the signals representing the balanced code, matched non-linear filtering on the signaling representing the balanced code to detect the presence of particular symbols and matched latching of the signals representing the balanced code. Such matched circuits and circuit components may be achieved at least in part by incorporating suitable common circuit nodes and/or a single energy source into circuit topologies.

Abstract: Methods and systems are disclosed for efficient cancellation of crosstalk between signals transmitted over multiple signal paths. Symmetry is induced on the signals transmitted over the signal paths such that the crosstalk matrix becomes a matrix with structure. Such structured matrix may be a circulant matrix of which the inverse may be applied efficiently to transmitted symbols or received symbols. Application of such inverse may comprise the fast Fourier transform. Applications of the methods and systems disclosed include chip-to-chip communications, on-chip communications, communication over cables and storage of information.

Abstract: In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a sparse signaling code, wherein a codeword is representable as a vector of a plurality of components, some of which are quiescent components and some of which are non-quiescent components, wherein the number of quiescent components and non-quiescent components meet a sparseness requirement.

Abstract: A sorting decoder captures the rank-order of a set of input analog signals in the digital domain using simple logic components such as self-timed first state elements, without requiring conventional analog-to-digital signal converters. The analog signals are each compared against a monotonic dynamic reference and the resulting comparisons are snapshot by a self-timed first state element for each input signal, or the last member of a sorted collection of input signals, at the time when it reaches the reference signal, so that a different snapshot representing the signal value ranking relative to the other signal values is produced for each input signal. The resulting rank-order estimation snapshots are binary signals that can then be further processed by a simple sorting logic circuit based on elementary logic components.

Abstract: Fixed capacitive circuits are described which perform arithmetical summation operations over sets of scaled analog values, where the constant parameters of the summations and scaling multiplications are formed as ratios of circuit element values. The passive nature of the design can enable efficient integrated circuit implementation.

Abstract: In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a spherical code, wherein a codeword is representable as a vector of a plurality of components and the bus uses at least as many signal lines as components of the vector that are used, mapping the codeword to a second set of physical signals, wherein components of the second set of physical signals can have values from a set of component values having at least three distinct values for at least one component, and providing the second set of physical signals for transmission over the data bus in a physical form.

Abstract: Digital information is communicated between stacked integrated circuit devices by inductive coupling between arrays of inductors formed from integrated circuit wiring layers. This can be done using a combination of push-pull drivers, common inductor return legs, and balanced sparse ternary encoding. Embodiments result in low power utilization and high pin efficiency.

Abstract: For digital data transmitted using a vector signaling encoding, a rank-order equalizer cancels various channel noise such as inter-symbol interference. Further, rank-order units may be cascaded to achieve improved equalization over successive sample vector signals in a rank-order equalizer. Multiple rank-order equalizers further operate in parallel in a feed forward mode or in series in a feedback mode to provide a continuous vector signaling stream equalization.

Abstract: Methods and circuits are described for creating low-weight codes, encoding of data as low-weight codes for communication or storage, and efficient decoding of low-weight codes to recover the original data. Low-weight code words are larger than the data values they encode, and contain a significant preponderance of a single value, such as zero bits. The resulting encoded data may be transmitted with significantly lower power and/or interference.

Abstract: A method is disclosed for storing information on non-volatile memory which can rewrite memory cells multiple times before a block needs to be erased. The information to be stored is transformed into a suitable form which has better robustness properties with respect to common sources of error, such as leakage of charge, or imperfect read/write units.

Abstract: For digital data transmitted using a vector signaling encoding, a rank-order equalizer cancels various channel noise such as inter-symbol interference. Further, rank-order units may be cascaded to achieve improved equalization over successive sample vector signals in a rank-order equalizer. Multiple rank-order equalizers further operate in parallel in a feed forward mode or in series in a feedback mode to provide a continuous vector signaling stream equalization.

Abstract: In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a sparse signaling code, wherein a codeword is representable as a vector of a plurality of components, some of which are quiescent components and some of which are non-quiescent components, wherein the number of quiescent components and non-quiescent components meet a sparseness requirement.