Abstract: A method, computer program product and computer system for trusted timestamping is provided. A processor generates a first key pair, where the key pair includes a public key and a private key. A processor publishes the public key of the first key pair to an immutable data structure. A processor receives a first digital file for timestamping. A processor signs the first digital file with the private key of the first key pair.

Abstract: A method, computer program product and computer system for trusted timestamping is provided. A processor generates a first key pair, where the key pair includes a public key and a private key. A processor publishes the public key of the first key pair to an immutable data structure. A processor receives a first digital file for timestamping. A processor signs the first digital file with the private key of the first key pair.

Abstract: A generic microprocessor architecture is provided with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.

Abstract: A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

Abstract: An approach is provided to determine the veracity of an online posting. In the approach, when a posting is received at a web site, a topic for the posting is automatically identified. The approach further identifies actions and corresponding action originators that have been taken to the posting, with the actions being events such as commenting, liking, disliking, re-sharing, posting the online posting. Veracity information is collected about the action originators. A veracity weighting for the action originators is assigned based on the collected veracity information.

Abstract: Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.

Abstract: A mechanism is provided for dictionary matching. The mechanism loads a plurality of dictionary memory arrays with a set of dictionary words and updates a plurality of status arrays. Each status array of the plurality of status arrays corresponds to a respective one of the plurality of dictionary memory arrays. Each entry of a given status array stores a status bit, which indicates whether a corresponding entry of the corresponding dictionary memory array stores a valid dictionary word. The mechanism receives an input data word and generates a hash value based on the input data word. The mechanism reads a dictionary word from each of the dictionary memory arrays and a status bit from each of the status arrays using the hash value as a read address. The mechanism determines whether a dictionary memory array within the plurality of dictionary memory arrays stores a valid dictionary word that matches the input data word.

Abstract: Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data.

Abstract: Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data.

Abstract: This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

Abstract: Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.

Abstract: A mechanism is provided for dictionary matching. The mechanism loads a plurality of dictionary memory arrays with a set of dictionary words and updates a plurality of status arrays. Each status array of the plurality of status arrays corresponds to a respective one of the plurality of dictionary memory arrays. Each entry of a given status array stores a status bit, which indicates whether a corresponding entry of the corresponding dictionary memory array stores a valid dictionary word. The mechanism receives an input data word and generates a hash value based on the input data word. The mechanism reads a dictionary word from each of the dictionary memory arrays and a status bit from each of the status arrays using the hash value as a read address. The mechanism determines whether a dictionary memory array within the plurality of dictionary memory arrays stores a valid dictionary word that matches the input data word.

Abstract: Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data.

Abstract: Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data.

Abstract: The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

Abstract: This disclosure describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization across physical boundaries that define physical partitions in a symmetric MCP. Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). The arrangement also enables MPEs to delegate functionality to one or more groups of SPEs such that those group(s) of SPEs may act as pseudo MPEs. Such delegation may occur across the physical boundaries. Regardless, the pseudo MPEs may utilize pseudo virtualized control threads to control the behavior of other groups of SPEs also across physical boundaries.

Abstract: This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

Abstract: A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

Abstract: This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

Abstract: A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.