Patents by Inventor Harm Peters
Harm Peters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20080256275Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.Type: ApplicationFiled: March 15, 2008Publication date: October 16, 2008Inventors: Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle
-
Publication number: 20080250414Abstract: A program is into at least two object files: one object file for each of the supported processor environments. During compilation, code characteristics, such as data locality, computational intensity, and data parallelism, are analyzed and recorded in the object file. During run time, the code characteristics are combined with runtime considerations, such as the current load on the processors and the size of the data being processed, to arrive at an overall value. The overall value is then used to determine which of the processors will be assigned the task. The values are assigned based on the characteristics of the various processors. For example, if one processor is better at handling intensive computations against large streams of data, programs that are highly computationally intensive and process large quantities of data are weighted in favor of that processor. The corresponding object is then loaded and executed on the assigned processor.Type: ApplicationFiled: May 7, 2008Publication date: October 9, 2008Inventors: Daniel Alan Brokenshire, Harm Peter Hofstee, Barry L. Minor, Mark Richard Nutter
-
Publication number: 20080235647Abstract: Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip.Type: ApplicationFiled: May 30, 2008Publication date: September 25, 2008Inventors: Harm Peter Hofstee, James Allan Kahle, Takeshi Yamazaki
-
Publication number: 20080222394Abstract: Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.Type: ApplicationFiled: May 21, 2008Publication date: September 11, 2008Inventors: Claude Basso, Jean Louis Calvignac, Chih-jen Chang, Gordon Taylor David, Harm Peter Hofstee, Fabrice Jean Verplanken, Colin Beaton Verrilli
-
Publication number: 20080189670Abstract: The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.Type: ApplicationFiled: April 1, 2008Publication date: August 7, 2008Inventors: Sang Hoo Dhong, Harm Peter Hofstee, Stephen Douglas Posluszny, Joel Abraham Silberman, Osamu Takahashi, Dieter F. Wendel
-
Patent number: 7409520Abstract: Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.Type: GrantFiled: January 25, 2005Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Claude Basso, Jean Louis Calvignac, Chih-jen Chang, Gordon Taylor Davis, Harm Peter Hofstee, Fabrice Jean Verplanken, Colin Beaton Verrilli
-
Patent number: 7406589Abstract: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.Type: GrantFiled: May 12, 2005Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Gordon Clyde Fossum, Harm Peter Hofstee, Brad William Michael, Silvia Melitta Mueller, Hwa-Joon Oh
-
Patent number: 7398482Abstract: Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip.Type: GrantFiled: July 28, 2005Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Harm Peter Hofstee, James Allan Kahle, Takeshi Yamazaki
-
Publication number: 20080162906Abstract: An approach to hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and/or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound.Type: ApplicationFiled: March 15, 2008Publication date: July 3, 2008Inventors: Daniel Alan Brokenshire, Harm Peter Hofstee, Barry L Minor, Mark Richard Nutter
-
Publication number: 20080162877Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.Type: ApplicationFiled: March 15, 2008Publication date: July 3, 2008Inventors: Erik Richter Altman, Peter George Capek, Michael Karl Gschwind, Charles Ray Johns, Harm Peter Hofstee, Martin E. Hopkins, James Allan Kahle, Sumedh W. Sathaye, John-David Wellman, Ravi Nair
-
Patent number: 7392511Abstract: A program is into at least two object files: one object file for each of the supported processor environments. During compilation, code characteristics, such as data locality, computational intensity, and data parallelism, are analyzed and recorded in the object file. During run time, the code characteristics are combined with runtime considerations, such as the current load on the processors and the size of the data being processed, to arrive at an overall value. The overall value is then used to determine which of the processors will be assigned the task. The values are assigned based on the characteristics of the various processors. For example, if one processor is better at handling intensive computations against large streams of data, programs that are highly computationally intensive and process large quantities of data are weighted in favor of that processor. The corresponding object is then loaded and executed on the assigned processor.Type: GrantFiled: September 25, 2003Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Daniel Alan Brokenshire, Harm Peter Hofstee, Barry L Minor, Mark Richard Nutter
-
Patent number: 7389419Abstract: The present invention provides for authenticating a message. A security function is performed upon the message. The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. The received message is authenticated as a function of at least a shared key, the received publicly known constants, the security function, the received message, and the output of the security function. If the output of the security function received by the target is the same as the output generated as a function of at least the received message, the received publicly known constants, the security function, and the shared key, neither the message nor the constants have been altered.Type: GrantFiled: December 10, 2003Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Daniel Alan Brokenshire, Harm Peter Hofstee, Mohammad Peyravian
-
Patent number: 7363609Abstract: The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.Type: GrantFiled: July 26, 2001Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, Stephen Douglas Posluszny, Joel Abraham Silberman, Osamu Takahashi, Dieter F. Wendel
-
Patent number: 7321958Abstract: A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.Type: GrantFiled: October 30, 2003Date of Patent: January 22, 2008Assignee: International Business Machines CorporationInventors: Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle
-
Patent number: 7299372Abstract: The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. The software is real time software, and the software also sets minimally acceptable activity control states. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.Type: GrantFiled: August 5, 2004Date of Patent: November 20, 2007Assignee: International Business Machines CorporationInventors: Jeffrey Douglas Brown, Michael Norman Day, Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle, Michael Fan Wang
-
Patent number: 7299371Abstract: The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.Type: GrantFiled: August 5, 2004Date of Patent: November 20, 2007Assignee: International Business Machines CorporationInventors: Micahel Norman Day, Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle
-
Patent number: 7279996Abstract: A method and apparatus is provided for testing the logic functionality and electrical continuity of a ring oscillator comprising an odd number of inverters connected to form a closed loop. In the method and apparatus, a known value is forced through the ring oscillator, to test the complete circuit path thereof. Thus, a low overhead deterministic test of the functionality of the ring oscillator is provided. In a useful embodiment of the invention, a method is provided for testing functionality and electrical continuity in a ring oscillator, wherein a first test device is inserted between the input of a first inverter and the output of an adjacent second inverter. The first test device is then operated to apply first and second test bits as input test signals to the first inverter input.Type: GrantFiled: August 16, 2005Date of Patent: October 9, 2007Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Harm Peter Hofstee, John Samuel Liberty
-
Patent number: 7233212Abstract: A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.Type: GrantFiled: March 31, 2005Date of Patent: June 19, 2007Assignee: International Business Machines CorporationInventors: David William Boerstler, Eskinder Hailu, Harm Peter Hofstee, John Samuel Liberty
-
Patent number: 7233998Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.Type: GrantFiled: March 22, 2001Date of Patent: June 19, 2007Assignees: Sony Computer Entertainment Inc., Kabushiki Kaisha Toshiba, International Business Machines CorporationInventors: Masakazu Suzuoki, Takeshi Yamazaki, Harm Peter Hofstee, Martin E. Hopkins, Charles Ray Johns, James Allan Kahle, Shigehiro Asano, Atsushi Kunimatsu
-
Patent number: 7200688Abstract: The present invention provides for asynchronous DMA command completion notification in a computer system. A command tag, associated with a plurality DMA command is generated. A DMA data movement command having the command tag is grouped with another DMA data movement command having the command tag. DMA commands belonging to the same tag group are monitored to see whether all DMA commands of the same tag group are completed.Type: GrantFiled: May 29, 2003Date of Patent: April 3, 2007Assignee: International Business Machines CorporationInventors: Michael Norman Day, Harm Peter Hofstee, Charles Ray Johns, Peichum Peter Liu, Thuong Quang Truong, Takeshi Yamazaki