Patents by Inventor Harm Peters
Harm Peters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6836849Abstract: A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system.Type: GrantFiled: April 5, 2001Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: Bishop Chapman Brock, Harm Peter Hofstee, Mark A. Johnson, Thomas Walter Keller, Jr., Kevin John Nowka
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Publication number: 20040249995Abstract: A system and a method are provided for improving memory management in a multiprocessor system. A direct memory access (DMA) operation is set up for a first processor. A DMA effective address is translated to a virtual address. The virtual address is translated to a physical address, which is used to access a memory hierarchy of the multiprocessor system.Type: ApplicationFiled: June 5, 2003Publication date: December 9, 2004Applicant: International Business Machines CorporationInventors: Michael Norman Day, Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle, David Shippy, Thuong Quang Truong
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Publication number: 20040243738Abstract: The present invention provides for asynchronous DMA command completion notification in a computer system. A command tag, associated with a plurality DMA command is generated. A DMA data movement command having the command tag is grouped with another DMA data movement command having the command tag. DMA commands belonging to the same tag group are monitored to see whether all DMA commands of the same tag group are completed.Type: ApplicationFiled: May 29, 2003Publication date: December 2, 2004Applicants: International Business Machines Corporation, Sony Computer Entertainment Inc.Inventors: Michael Norman Day, Harm Peter Hofstee, Charles Ray Johns, Peichum Peter Liu, Thuong Quang Truong, Takeshi Yamazaki
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Patent number: 6826110Abstract: An improved cell circuit for data readout with reduced number of read wordlines is provided in a memory block of a multiport memory array. The number of read wordlines is significantly reduced by using a decoder between the read wordlines and a multiplexer in the cell circuit. The memory block has a plurality of address inputs and stores a plurality of write data signals. In the cell circuit, the decoder receives as decoder inputs a subset of the address inputs and outputs a plurality of select signals. The multiplexer is coupled to the decoder to receive the select signals and select one of the write data signals based on the select signals. Additionally, the read wordlines are coupled to the decoder for carrying the subset of the address inputs to the decoder.Type: GrantFiled: October 17, 2002Date of Patent: November 30, 2004Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, Shoji Onishi, Osamu Takahashi
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Patent number: 6820142Abstract: A method and system for accessing a shared memory in a deterministic schedule. In one embodiment, a system comprises a plurality of processing elements and a system I/O controller where each processing element and system I/O controller comprises a DMA controller. The system further comprises a shared memory coupled to each of the plurality of processing elements where the shared memory comprises a master controller. The master controller may then issue tokens to DMA controllers to grant the right for the associated processing elements and system I/O controller to access the shared memory at deterministic points in time. Each token issued by the master controller grants access to the shared memory for a particular duration of time at a unique deterministic point in time. A processing element or system I/O controller may access the shared memory upon the associated DMA controller relinquishing to the master controller the token that grants the right to access the shared memory at that particular time.Type: GrantFiled: December 14, 2000Date of Patent: November 16, 2004Assignee: International Business Machines CorporationInventors: Harm Peter Hofstee, Ravi Nair, John-David Wellman
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Publication number: 20040221086Abstract: A first device is operable to communicate on an bus according to a first protocol. A bridge is also operable to communicate on the bus according to the first protocol. A second device is coupled to the bus via the bridge and operable to communicate according to a second protocol. The bridge has a memory for holding data received from the second device and is operable to translate from the second to the first protocol. The second device sends write data responsive to receiving a ready signal from the bridge, and includes memory for holding the write data that the second device has sent, but for which completion has not been signaled. The second device re-sends the write data from the memory responsive to receiving a non-completion signal via the bridge, and releases the memory for the data responsive to receiving a completion signal via the bridge.Type: ApplicationFiled: April 17, 2003Publication date: November 4, 2004Applicant: International Business Machines CorporationInventors: Bernard Charles Drerup, Harm Peter Hofstee, Wendel Glenn Voigt, Barry Joe Wolford
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Publication number: 20040201970Abstract: Disclosed is an apparatus which shows the use of an inwardly disposed set of C4 type I/O connections to an integrated circuit chip over and above the typical peripherally disposed set of I/O connections which use wire type connections between the chip and other circuitry of a substrate upon which the chip is mounted. The inwardly disposed set of connections may be used to provide a direct connection to an optional ancillary chip having a corresponding set of I/O connection points. Such a construction not only increases the number of possible I/O connections, but additionally increases the bandwidth of communications between the directly connected chips.Type: ApplicationFiled: April 10, 2003Publication date: October 14, 2004Applicant: International Business Machines CorporationInventors: Paul Marlan Harvey, Harm Peter Hofstee, James Allan Kahle, Gordon J. Robbins
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Patent number: 6785841Abstract: A system including a central processor and a plurality of attached processors all on a single die are disclosed. Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be substantially equivalent to each of the attached processors. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. The attached processors may be connected to a memory interface unit via a parallel bus or a pipelined bus in which each attached processor is connected to a stage of the pipelined bus. The attached processors may each include a load/store unit and logic suitable for performing a mathematical function.Type: GrantFiled: December 14, 2000Date of Patent: August 31, 2004Assignee: International Business Machines CorporationInventors: Chekib Akrout, Harm Peter Hofstee, James Allan Kahle
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Publication number: 20040160835Abstract: A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.Type: ApplicationFiled: February 19, 2004Publication date: August 19, 2004Inventors: Erik R. Altman, Peter G. Capek, Michael Karl Gschwind, Harm Peter Hofstee, James Allan Kahle, Ravi Nair, Sumedh Wasudeo Sathaye, John-David Wellman
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Patent number: 6779049Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.Type: GrantFiled: December 14, 2000Date of Patent: August 17, 2004Assignee: International Business Machines CorporationInventors: Erik R. Altman, Peter G. Capek, Michael Gschwind, Harm Peter Hofstee, James Allan Kahle, Ravi Nair, Sumedh Wasudeo Sathaye, John-David Wellman, Masakazu Suzuoki, Takeshi Yamazaki
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Patent number: 6772368Abstract: In one embodiment a multiprocessing apparatus includes a first processor and a second processor. Each of the processors have their own data and instruction caches to support independent operation. In a normal mode the processors independently execute separate instruction streams. Each of the processors has a respective signature generator. The system also includes a compare unit coupled to the signature generators. In a high reliability mode, both processors execute the same instruction stream. That is, each processor computes a version of a result for ones of the instructions in the stream. Responsive to the respective versions, the respective signature generators assert signatures to the compare unit, so that a faulting instruction may be detected. In another aspect, each processor has its own respective commit logic.Type: GrantFiled: December 11, 2000Date of Patent: August 3, 2004Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, Ravi Nair, Steven Douglas Posluszny
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Patent number: 6760819Abstract: A processor-cache operational scheme and topology within a multi-processor data processing system having a shared lower level cache (or memory) by which the number of coherency busses is reduced and more efficient snoop resolution and coherency operations with the processor caches are provided. A copy of the internal (L1) cache directory is provided within the lower level (L2) cache or memory. The snoop operations and coherency maintenance operations of the L1 directory are completed by comparing the snoop addresses with the address tags of the copy of the L1 directory in the L2 cache. Updates to the coherency states of the copy of the L1 directory are mirrored in the L1 directory and L1 cache. This eliminates the need for the individual coherency buses of each processor that is coupled to the L2 cache and speeds up coherency operations because the snoops do not have to be transmitted to the L1 caches.Type: GrantFiled: June 29, 2001Date of Patent: July 6, 2004Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, Charles Ray Johns, John Samuel Liberty, Thuong Quang Truong
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Publication number: 20040117592Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.Type: ApplicationFiled: December 12, 2002Publication date: June 17, 2004Applicant: International Business Machines CorporationInventors: Michael Norman Day, Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle, David Shippy, Thuong Quang Truong
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Patent number: 6751749Abstract: According to one embodiment, a multiprocessing system includes a first processor, a second processor, and compare logic. The first processor is operable to compute first results responsive to instructions, the second processor is operable to compute second results responsive to the instructions, and the compare logic is operable to check at checkpoints for matching of the results. Each of the processors has a first register for storing one of the processor's results, and the register has a stack of shadow registers. The processor is operable to shift a current one of the processor's results from the first register into the top shadow register, so that an earlier one of the processor's results can be restored from one of the shadow registers to the first register responsive to the compare logic determining that the first and second results mismatch. It is advantageous that the shadow register stack is closely coupled to its corresponding register, which provides for fast restoration of results.Type: GrantFiled: February 22, 2001Date of Patent: June 15, 2004Assignee: International Business Machines CorporationInventors: Harm Peter Hofstee, Ravi Nair
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Publication number: 20040111546Abstract: The present invention provides a data access ring. The data access ring has a plurality of attached processor units (APUs) and a local store associated with each APU. The data access ring has a data command ring, coupled to the plurality of APUs. The data command ring is employable to carry indicia of a selection of one of the plurality of APUs to the APUs. The data access ring also has a data address ring, coupled to the plurality of APUs. The data address ring is further employable to carry indicia of a memory location to the selected APU a predetermined number of clock cycles after the data command ring carries the indicia of the selection of one of the plurality of APUs. The data access ring also has a data transfer ring, coupled to the plurality of APUs. The data transfer ring is employable to transfer data to or from the memory location associated with the APU a predetermined number of clock cycles after the data address ring carries the indicia of the memory location to the selected APU.Type: ApplicationFiled: December 5, 2002Publication date: June 10, 2004Applicant: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, John Samuel Liberty, Peichun Peter Liu
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Publication number: 20040107321Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.Type: ApplicationFiled: October 1, 2003Publication date: June 3, 2004Inventors: Erik R. Altman, Peter G. Capek, Michael Karl Gschwind, Harm Peter Hofstee, James Allan Kahle, Ravi Nair, Sumedh Wasudeo Sathaye, John-David Wellman
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Method and apparatus for verifying that instructions are pipelined in correct architectural sequence
Patent number: 6728872Abstract: A method and apparatus for enabling the correct architectural sequencing of fetched instructions prior to allowing the instructions to complete in the processor pipeline to reduce the occurrence of pipeline breaks. A branch processing unit (BPU) is designed to perform sequence checks for the addresses of all instructions fetched into the pipeline (i.e., both in-line and branch instructions) by the instruction fetch unit (IFU). A first instruction is fetched. The address of the next instruction in the architectural sequence is computed and stored within the BPU. The next instruction is fetched and its address is compared to the next instruction address stored in BPU to determine if it is the correct address. If the next instruction address matches that of the architectural sequence, the instruction is permitted to “live” (i.e., continue through to completion). When the address does not match, the instruction is killed (i.e., not allowed to complete) and a new instruction is fetched by the IFU.Type: GrantFiled: February 4, 2000Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Brian King Flacks, Harm Peter Hofstee -
Publication number: 20040078613Abstract: Disclosed is an electronic chip containing a plurality of electronic circuit partitions, distributed over the area of the chip, each including a processor core and a clock phase domain different from cores in other partitions of the chip. A source of same frequency, but different phase clock signals representing different clock domains, provides different phase signals to adjacent partitions for the purpose of reducing instantaneous magnitude switching currents. Intra-chip communication circuitry distributes control and data signals between partitions.Type: ApplicationFiled: October 17, 2002Publication date: April 22, 2004Applicant: International Business Machines CorporationInventors: David William Boerstler, Sang Hoo Dhong, Harm Peter Hofstee, Peichun Peter Liu
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Publication number: 20040076063Abstract: An improved cell circuit for data readout with reduced number of read wordlines is provided in a memory block of a multiport memory array. The number of read wordlines is significantly reduced by using a decoder between the read wordlines and a multiplexer in the cell circuit. The memory block has a plurality of address inputs and stores a plurality of write data signals. In the cell circuit, the decoder receives as decoder inputs a subset of the address inputs and outputs a plurality of select signals. The multiplexer is coupled to the decoder to receive the select signals and select one of the write data signals based on the select signals. Additionally, the read wordlines are coupled to the decoder for carrying the subset of the address inputs to the decoder.Type: ApplicationFiled: October 17, 2002Publication date: April 22, 2004Applicant: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, Shoji Onishi, Osamu Takahashi
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Publication number: 20040076064Abstract: An improved cell circuit for data readout for use in a multiport memory is provided. The multiport memory stores write data signals. The cell circuit includes a plurality of multiplexers each coupled to a discharge device. Each of the multiplexers receives a subset of the write data signals and a plurality of read wordline signals and selects an output enable signal among the subset of the write data signals based on the read wordline signals. Each of the discharge devices are coupled to one of the multiplexers for receiving the output enable signal to generate a drive signal for driving one or more bitlines of the multiport memory.Type: ApplicationFiled: October 17, 2002Publication date: April 22, 2004Applicant: International Business Machines CorporationInventors: Sang Hoo Dhong, Harm Peter Hofstee, Shoji Onishi, Osamu Takahashi