Abstract: A system for interference detection includes one or more processors are configured to receive from one or more access points within a wireless network information indicative of airtime usage of one or more client devices associated with the one or more access points, determine an amount of total interference for at least one of the access points on a first channel, the total interference including foreign interference and in-network interference, determine a correlation between the total interference and the airtime usage of the one or more client devices, determine an amount of the foreign interference or an amount of the in-network interference based on the correlation, and selectively switch the at least one of the access points from communicating on the first channel to communicating on a second channel based on the determined amount of the foreign interference or the determined amount of the in-network interference.

Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. The area comprises a plurality of pixels, and the original set of exposure information comprises dosages for the plurality of pixels in the area. A backscatter is calculated for a sub area of the area based on the original set of exposure information including the dosages for the plurality of pixels in the area. An increase in dosage for at least one pixel in a plurality of pixels in the sub area is determined, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area.

Abstract: Methods for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area, based on an original set of exposure information. A pre-proximity effect correction (PEC) maximum dose for the local pattern density is determined, based on a pre-determined target post-PEC maximum dose. The pre-PEC maximum dose is calculated near an edge of the desired shape. Methods also include modifying the original set of exposure information with the pre-PEC maximum dose to create a modified set of exposure information.

Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. The area comprises a plurality of pixels, and the original set of exposure information comprises dosages for the plurality of pixels in the area. A backscatter is calculated for a sub area of the area based on the original set of exposure information. A dosage for at least one pixel in a plurality of pixels in the sub area is increased, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area. A modified set of exposure information is output, including the increased dosage of the at least one pixel in the sub area.

Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. A backscatter is calculated for the area of the pattern based on the exposure information. An artificial background dose is determined for the area. The artificial background dose comprises additional exposure information and is combined with the original set of exposure information creating a modified set of exposure information. A system for exposing a pattern in an area on a surface using a charged particle beam lithography is also disclosed.

Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be coupled to a processor, which includes a memory controller. The memory controller may determine whether targeting of first data and second data by the processor to perform an operation results in processor-side cache misses. When targeting of the first data and the second data result in processor-side cache misses, the memory controller may determine a single memory access request that requests return of both the first data and the second data and instruct the processor to output the single memory access request to a memory system via one or more data buses coupled between the processor and the memory system to enable processing circuitry implemented in the processor to perform the operation based at least in part on the first data and the second data when returned from the memory system.

Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be communicative coupled to a processor via one or more data buses. Additionally, the memory system may include one or more memory devices that store data to be used by processing circuitry implemented in the processor to perform an operation. Furthermore, the memory system may include a memory controller that receives a memory access request that return of the data via the one or more data buses and, in response, determines a storage location of the data in the one or more memory devices based at least in part on the memory access request and instructs the memory system to store the data directly into a processor-side cache integrated with the processing circuitry to enable the processing circuitry implemented in the processor to perform the operation based on the data.

Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be communicative coupled to a processor via one or more data buses. Additionally, the memory system may include one or more memory devices that store data to be used by processing circuitry implemented in the processor to perform an operation. Furthermore, the memory system may include a memory controller that receives a memory access request that requests return of the data via the one or more data buses and, in response, determines a storage location of the data in the one or more memory devices based at least in part on the memory access request and instructs the memory system to store the data directly into a processor-side cache integrated with the processing circuitry to enable the processing circuitry implemented in the processor to perform the operation based on the data.

Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be coupled to a processor, which includes a memory controller. The memory controller may determine whether targeting of first data and second data by the processor to perform an operation results in processor-side cache misses. When targeting of the first data and the second data result in processor-side cache misses, the memory controller may determine a single memory access request that requests return of both the first data and the second data and instruct the processor to output the single memory access request to a memory system via one or more data buses coupled between the processor and the memory system to enable processing circuitry implemented in the processor to perform the operation based at least in part on the first data and the second data when returned from the memory system.

Abstract: Techniques are described for configuring an optical network unit (ONU) in a pre-burst state prior to transitioning the ONU to a burst-on state. During the pre-burst state, a laser emitter of the ONU stabilizes to its wavelength, thereby reducing the impact of wavelength drift when the ONU transitions to the burst-on state.

Abstract: The present disclosure includes systems, apparatuses and methods related to maintaining data in a sorted order in a memory array to improve access time to data in the memory array and directing access to a row of data in cache based upon an address associated with the data. In a number of embodiments, a number of keys that are stored in a first row of an index table can be split between the first row and a second row in response to the first row being full, where the number of keys are copied to the second row and a first portion of the number of keys remain in the first row and a second portion of the number of keys are moved to the second row.

Abstract: The present disclosure includes systems, apparatuses and methods related to maintaining data in a sorted order in a memory array to improve access time to data in the memory array and directing access to a row of data in cache based upon an address associated with the data. In a number of embodiments, data can be sorted by receiving a portion of data for storage in a memory device, extracting a key associated with the portion of data, determining a row of an index table to store the key, and placing the key along with a number of keys in the row of the index table in a sorted order, wherein the sorted order is in relation to keys associated with portions of data previously stored in the memory device.

Abstract: Methods, apparatuses, and systems related to mapping a virtual address using a physical address are described. In a memory system including a memory (e.g., cache) and a content addressable memory (CAM), the CAM can be configured to search data requested by a host from the memory based on multiple indicators stored in the CAM. For example, in the event that the data stored in the memory is not searchable based on a particular indicator such as a virtual address of a memory array (e.g., main memory), the CAM be configured to search the data based on another indicator such as a physical address of the memory array. Searching the data based on multiple indicators can resolve a synonym problem.

Abstract: The present disclosure includes systems, apparatuses and methods related to maintaining data in a sorted order in a memory array to improve access time to data in the memory array and directing access to a row of data in cache based upon an address associated with the data. In a number of embodiments, data stored in tables in sorted order can allow access to data based on upon the keys and/or the sorted order of the data, which can increase access times to data the memory array.

Abstract: Apparatuses, systems, and methods for mapping a virtual address using a CAM are described. A parallel structure of a CAM can enable functions of a MMU to be integrated into a single operation performed using the CAM such that a virtual address of a memory array can be mapped directly to a row of a memory. An example method includes receiving an access command and address information for a memory array; identifying a virtual address and a physical address of the memory array based on the received address information; comparing, during a time period associated with the access command, the virtual address and the physical address to virtual addresses and physical addresses, respectively, of the memory array stored in a CAM; and accessing, during the time period, a row of the memory array coupled to a row of the CAM storing the virtual address and the physical address.

Abstract: Methods, apparatuses, and systems related to mapping a virtual address using a content addressable memory (CAM) are described. In a memory system including a memory and a content addressable memory (CAM), a select line of the CAM can be coupled to a corresponding select line of the memory, which allows the memory system to map a virtual address of a memory device directly to the corresponding select line of the memory. An example method can include receiving, from a host at a memory device comprising a memory array and a content addressable memory (CAM), a first virtual address to be searched among virtual addresses stored within the CAM, identifying, in response to receipt of the first virtual address, a select line of a plurality of select lines of the CAM associated with a second virtual address matching the first virtual address, and activating, in response to identifying the select line of the CAM, a corresponding select line of the memory coupled to the identified select line of the CAM.

Abstract: Methods for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area of the desired shape based on an original set of exposure information. A backscatter for a sub area is calculated, based on the original set of exposure information. Dosage for at least one pixel in a plurality of pixels in the sub area is increased, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area. A pre-PEC maximum dose is determined for the local pattern density, based on a pre-determined target post-PEC maximum dose. The original set of exposure information is modified with the pre-PEC maximum dose and the increased dosage of the at least one pixel in the sub area to create a modified set of exposure information.

Abstract: Methods include inputting an array of pixels, where each pixel in the array of pixels has a pixel dose. The array of pixels represents dosage on a surface to be exposed with a plurality of patterns, each pattern of the plurality of patterns having an edge. A target bias is input. An edge of a pattern in the plurality of patterns is identified. For each pixel which is in a neighborhood of the identified edge, a calculated pixel dose is calculated such that the identified edge is relocated by the target bias. The array of pixels with the calculated pixel doses is output. Systems for performing the methods are also disclosed.

Abstract: A power generation system (100, 200, 300, 400) is presented. The power generation system includes a prime mover (102), a doubly-fed induction generator (DFIG) (104) having a rotor winding (126) and a stator winding (122), a rotor-side converter (106), a line-side converter (108), and a secondary power source (110, 401) electrically coupled to a DC-link (128). Additionally, the power generation system includes a control sub-system (112, 212, 312) having a controller, and a plurality of switching elements (130, and 132 or 201). The controller is configured to selectively control switching of one or more switching elements (130, and 132 or 201) based on a value of an operating parameter corresponding to at least one of the prime mover, the DFIG, or the secondary power source to connect the rotor-side converter in parallel to the line-side converter to increase an electrical power production by the power generation system.

Abstract: An electrical power system connectable to a power grid includes a cluster of electrical power subsystems, each of the electrical power subsystems including a power converter electrically coupled to a generator having a generator rotor and a generator stator. Each of the electrical power subsystems defines a stator power path and a converter power path for providing power to the power grid. Each of the electrical power subsystems further includes a transformer. The system further includes a subsystem breaker configured with each of the electrical power subsystems, and a cluster power path extending from each subsystem breaker for connecting the cluster of electrical power subsystems to the power grid. The system further includes a reactive power compensation inverter electrically coupled within the electrical power system, the reactive power compensation inverter operable to increase the reactive power level in the electrical current flowing to the power grid.