Patents by Inventor Harold B. Noyes

Harold B. Noyes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and systems for using state vector data in a state machine engine
    Patent number: 10489062
    Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes
  • DEVICES, SYSTEMS, AND METHODS TO SYNCHRONIZE SIMULTANEOUS DMA PARALLEL PROCESSING OF A SINGLE DATA STREAM BY MULTIPLE DEVICES
    Publication number: 20190354530
    Abstract: Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.
    Type: Application
    Filed: July 31, 2019
    Publication date: November 21, 2019
    Inventor: Harold B Noyes
  • SYSTEMS AND DEVICES FOR ACCESSING A STATE MACHINE
    Publication number: 20190354380
    Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 21, 2019
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning
  • METHODS AND APPARATUSES FOR PROVIDING DATA RECEIVED BY A STATE MACHINE ENGINE
    Publication number: 20190347233
    Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.
    Type: Application
    Filed: July 23, 2019
    Publication date: November 14, 2019
    Inventors: David R. Brown, Harold B. Noyes, Inderjit S. Bains
  • BUS TRANSLATOR
    Publication number: 20190340454
    Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.
    Type: Application
    Filed: July 17, 2019
    Publication date: November 7, 2019
    Inventors: Harold B Noyes, Steven P. King
  • METHODS AND SYSTEMS FOR HANDLING DATA RECEIVED BY A STATE MACHINE ENGINE
    Publication number: 20190340130
    Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 7, 2019
    Inventors: David R. Brown, Harold B Noyes, Inderjit Singh Bains
  • Systems and methods to enable identification of different data sets
    Patent number: 10466966
    Abstract: Systems and methods are provided, such as those that enable identification of data flows and corresponding results in a pattern-recognition processor. In one embodiment, a system may include the pattern-recognition processor and a flow identification register, wherein a unique flow identifier for each data flow is stored in the register. The system may include a results buffer that stores the results data and the flow identifier for each data flow, so that the results data may be related to a specific data flow.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Harold B Noyes
  • Systems and devices for accessing a state machine
    Patent number: 10430210
    Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning
  • Devices, systems, and methods to synchronize simultaneous DMA parallel processing of a single data stream by multiple devices
    Patent number: 10417236
    Abstract: Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Harold B Noyes
  • Validation of a symbol response memory
    Patent number: 10402265
    Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning
  • SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING
    Publication number: 20190258592
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • Bus translator
    Patent number: 10380446
    Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, Steven P. King
  • Apparatuses for providing data received by a state machine engine
    Patent number: 10372653
    Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes, Inderjit S. Bains
  • METHODS AND SYSTEMS FOR USING STATE VECTOR DATA IN A STATE MACHINE ENGINE
    Publication number: 20190235766
    Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Inventors: David R. Brown, Harold B Noyes
  • Methods and systems for handling data received by a state machine engine
    Patent number: 10366009
    Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes, Inderjit Singh Bains
  • System and method for individual addressing
    Patent number: 10339071
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • ADAPTIVE CONTENT INSPECTION
    Publication number: 20190180191
    Abstract: Methods and apparatus are provided involving adaptive content inspection. In one embodiment, a content inspection processor may identify information with respect to input data and provide the information to a host controller. The host controller may adapt search criteria or other parameters and provide the adapted parameter to the content inspection processor. Other embodiments may include a content inspection processor having integrated feedback, such that results data is fed back to the content inspection processor. The results data may be processed before being provided to the content inspection processor.
    Type: Application
    Filed: February 20, 2019
    Publication date: June 13, 2019
    Inventors: Paul D. Dlugosch, Harold B Noyes
  • METHODS AND SYSTEMS FOR DEVICES WITH SELF-SELECTING BUS DECODER
    Publication number: 20190146937
    Abstract: Disclosed are methods and devices, among which is a device that uses a memory map to identify whether functionality of the device should be implemented. The device may be coupled to a separate device, and, in some embodiments, the device may determine and provide a response of the device to requests from the separate device.
    Type: Application
    Filed: January 14, 2019
    Publication date: May 16, 2019
    Inventors: Harold B Noyes, Stephen P. King
  • System and method for individual addressing
    Patent number: 10268602
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • Methods and systems for using state vector data in a state machine engine
    Patent number: 10254976
    Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: April 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes