Patents by Inventor Harold B. Noyes

Harold B. Noyes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DEVICES, SYSTEMS, AND METHODS TO SYNCHRONIZE SIMULTANEOUS DMA PARALLEL PROCESSING OF A SINGLE DATA STREAM BY MULTIPLE DEVICES
    Publication number: 20190095496
    Abstract: Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Inventor: Harold B Noyes
  • METHODS AND APPARATUSES FOR REDUCING POWER CONSUMPTION IN A PATTERN RECOGNITION PROCESSOR
    Publication number: 20190095497
    Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: Harold B Noyes, David R. Brown
  • SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING
    Publication number: 20190087360
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Application
    Filed: December 10, 2018
    Publication date: March 21, 2019
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B. Noyes
  • Adaptive content inspection
    Patent number: 10235627
    Abstract: Methods and apparatus are provided involving adaptive content inspection. In one embodiment, a content inspection processor may identify information with respect to input data and provide the information to a host controller. The host controller may adapt search criteria or other parameters and provide the adapted parameter to the content inspection processor. Other embodiments may include a content inspection processor having integrated feedback, such that results data is fed back to the content inspection processor. The results data may be processed before being provided to the content inspection processor.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: March 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Paul D. Dlugosch, Harold B Noyes
  • Methods and systems for devices with self-selecting bus decoder
    Patent number: 10180922
    Abstract: Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: January 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, Steven P. King
  • Devices, systems, and methods to synchronize simultaneous DMA parallel processing of a single data stream by multiple devices
    Patent number: 10162862
    Abstract: Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Harold B Noyes
  • Methods and apparatuses for reducing power consumption in a pattern recognition processor
    Patent number: 10157208
    Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown
  • METHODS AND APPARATUSES FOR PROVIDING DATA RECEIVED BY A STATE MACHINE ENGINE
    Publication number: 20180341612
    Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.
    Type: Application
    Filed: August 2, 2018
    Publication date: November 29, 2018
    Inventors: David R. Brown, Harold B. Noyes, Inderjit S. Bains
  • VALIDATION OF A SYMBOL RESPONSE MEMORY
    Publication number: 20180322006
    Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 8, 2018
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning
  • SYSTEMS AND METHODS TO ENABLE IDENTIFICATION OF DIFFERENT DATA SETS
    Publication number: 20180307463
    Abstract: Systems and methods are provided, such as those that enable identification of data flows and corresponding results in a pattern-recognition processor. In one embodiment, a system may include the pattern-recognition processor and a flow identification register, wherein a unique flow identifier for each data flow is stored in the register. The system may include a results buffer that stores the results data and the flow identifier for each data flow, so that the results data may be related to a specific data flow.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventor: Harold B Noyes
  • Methods and apparatuses for providing data received by a state machine engine
    Patent number: 10067901
    Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: September 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: David R. Brown, Harold B Noyes, Inderjit S. Bains
  • BUS TRANSLATOR
    Publication number: 20180247144
    Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.
    Type: Application
    Filed: April 30, 2018
    Publication date: August 30, 2018
    Inventors: Harold B. Noyes, Steven P. King
  • Validation of a symbol response memory
    Patent number: 10019311
    Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 10, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning
  • Indirect register access method and system
    Patent number: 10020033
    Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: July 10, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, Mark Jurenka, Gavin Huggins
  • Systems and methods to enable identification of different data sets
    Patent number: 10007486
    Abstract: Systems and methods are provided, such as those that enable identification of data flows and corresponding results in a pattern-recognition processor. In one embodiment, a system may include the pattern-recognition processor and a flow identification register, wherein a unique flow identifier for each data flow is stored in the register. The system may include a results buffer that stores the results data and the flow identifier for each data flow, so that the results data may be related to a specific data flow.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Harold B Noyes
  • METHODS AND SYSTEMS FOR DATA ANALYSIS IN A STATE MACHINE
    Publication number: 20180137416
    Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.
    Type: Application
    Filed: January 15, 2018
    Publication date: May 17, 2018
    Inventors: David R. Brown, Harold B Noyes
  • Bus translator
    Patent number: 9959474
    Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: May 1, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, Steven P. King
  • VALIDATION OF A SYMBOL RESPONSE MEMORY
    Publication number: 20180089019
    Abstract: Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment, a device includes a plurality of blocks, each block of the plurality of blocks includes a plurality of rows, each row of the plurality of rows includes a plurality of configurable elements, each configurable element of the plurality of configurable elements includes a data analysis element including a memory component programmed with configuration data. The data analysis element is configured to analyze at least a portion of a data stream based on the configuration data and to output a result of the analysis. The device also includes an error detection engine (EDE) configured to perform integrity validation of the configuration data.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning
  • SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING
    Publication number: 20180089113
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • Methods and Devices for Saving and/or Restoring a State of a Pattern-Recognition Processor
    Publication number: 20180075165
    Abstract: Systems and methods are disclosed for saving and restoring the search state of a pattern-recognition processor. Embodiments include a pattern-recognition processor having a state variable array and a state variable storage array stored in on-chip memory (on-silicon memory with the processor). State variable storage control logic of the pattern-recognition processor may control the saving of state variables from the state variable array to the state variable storage array. The state variable storage control logic may also control restoring of the state variables from the state variable storage array to restore a search state.
    Type: Application
    Filed: November 7, 2017
    Publication date: March 15, 2018
    Inventors: Harold B. Noyes, David R. Brown