Patents by Inventor Harold Robert Feldman Zatz
Harold Robert Feldman Zatz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8730252Abstract: A system, method and computer program product are provided for bump mapping in a hardware graphics processor. Initially, a first set of texture coordinates is received. The texture coordinates are then multiplied by a matrix to generate results. A second set of texture coordinates is then offset utilizing the results. The offset second set of texture coordinates is then mapped to color.Type: GrantFiled: March 31, 2004Date of Patent: May 20, 2014Assignee: NVIDIA CorporationInventors: Henry P. Moreton, John Erik Lindholm, Matthew N. Papakipos, Harold Robert Feldman Zatz
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Patent number: 7928997Abstract: Digital Image compositing using a programmable graphics processor is described. The programmable graphics processor supports high-precision data formats and can be programmed to complete a plurality of compositing operations in a single pass through a fragment processing pipeline within the programmable graphics processor. Source images for one or more compositing operations are stored in graphics memory, and a resulting composited image is output or stored in graphics memory. More-complex compositing operations, such as blur, warping, morphing, and the like, can be completed in multiple passes through the fragment processing pipeline. A composited image produced during a pass through the fragment processing pipeline is stored in graphics memory and is available as a source image for a subsequent pass.Type: GrantFiled: May 21, 2003Date of Patent: April 19, 2011Assignee: NVIDIA CorporationInventors: Rui M. Bastos, Daniel Elliott Wexler, Larry Gritz, Jonathan Rice, Harold Robert Feldman Zatz, Matthew N. Papakipos, David Kirk
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Patent number: 7911471Abstract: A method and apparatus for executing loop and branch program instructions in a programmable graphics shader. The programmable graphics shader converts a sequence of instructions comprising a portion of a shader program and selects a first set of fragments to be processed. Subsequent sequences of instructions are converted until all of the instructions comprising the shader program have been executed on the first set of fragments. Each remaining set of fragments is processed by the shader program until all of the fragments are processed in the same manner. Furthermore, the instructions can contain one or more loop or branch program instructions that are conditionally executed. Additionally, when instructions within a loop as defined by a loop instruction are being executed a current loop count is pipelined through the programmable graphics shader and used as an index to access graphics memory.Type: GrantFiled: October 8, 2004Date of Patent: March 22, 2011Assignee: NVIDIA CorporationInventors: Roger L. Allen, Harold Robert Feldman Zatz
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Patent number: 7889208Abstract: A system, method and computer program product are provided for computer graphics processing. In use, a value is modified based on an algorithm. An operation is subsequently performed on pixel data taking into account the modified value.Type: GrantFiled: March 18, 2004Date of Patent: February 15, 2011Assignee: NVIDIA CorporationInventors: Henry P. Moreton, John Erik Lindholm, Matthew N. Papakipos, Harold Robert Feldman Zatz
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Patent number: 7477266Abstract: Digital Image compositing using a programmable graphics processor is described. The programmable graphics processor supports high-precision data formats and can be programmed to complete a plurality of compositing operations in a single pass through a fragment processing pipeline within the programmable graphics processor. Source images for one or more compositing operations are stored in graphics memory, and a resulting composited image is output or stored in graphics memory. More-complex compositing operations, such as blur, warping, morphing, and the like, can be completed in multiple passes through the fragment processing pipeline. A composited image produced during a pass through the fragment processing pipeline is stored in graphics memory and is available as a source image for a subsequent pass.Type: GrantFiled: September 24, 2004Date of Patent: January 13, 2009Assignee: NVIDIA CorporationInventors: Rui M. Bastos, Daniel Elliott Wexler, Larry Gritz, Jonathan Rice, Harold Robert Feldman Zatz, Matthew N. Papakipos, David Kirk
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Patent number: 7477255Abstract: A method for synchronizing divergent samples in a programmable graphics processing unit is described. In one embodiment, the method includes the steps of determining that a divergence has occurred and detecting that a first sample of a group of samples has encountered a first synch token. The method also includes the steps of determining whether each of the other samples of the group has encountered a synch token and determining whether the synch token encountered by each of the other samples of the group is the first synch token.Type: GrantFiled: April 12, 2004Date of Patent: January 13, 2009Assignee: NVIDIA CorporationInventors: John Erik Lindholm, Harold Robert Feldman Zatz, Christian Rouet, Rui M. Bastos
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Patent number: 7358970Abstract: A method and apparatus for generating depth values in a programmable graphics system. Depth values are calculated under control of a pixel program using a variety of sources as inputs to programmable computation units (PCUs) in the programmable graphics system. The PCUs are used to compute traditional interpolated depth values and modified depth values. The PCUs are also used to compute arbitrary depth values which, unlike traditional interpolated depth values and modified depth values, are not dependent on the coordinates of the geometry primitive with which the arbitrary depth values are associated. Several sources are available as inputs to the PCUs. Clipping with optional clamping is performed using either interpolated depth values or calculated depth values, where calculated depth values are arbitrary depth values or modified depth values. Final depth values, used for depth testing, are selected from interpolated depth values and arbitrary depth values after clipping is performed.Type: GrantFiled: September 28, 2004Date of Patent: April 15, 2008Assignee: NVIDIA CorporationInventor: Harold Robert Feldman Zatz
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Patent number: 7324112Abstract: A method for processing divergent samples in a programmable graphics processing unit is described. In one embodiment, the method includes the step of incrementing a subroutine depth of a first sample to designate that first call instructions are to be executed on the first sample. The method also includes the steps of pushing state data of a second sample upon which the first call instructions are not to be executed onto a global stack and executing the first call instructions on the first sample.Type: GrantFiled: April 12, 2004Date of Patent: January 29, 2008Assignee: NVIDIA CorporationInventors: John Erik Lindholm, Harold Robert Feldman Zatz, Christian Rouet, Rui M. Bastos
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Patent number: 7274373Abstract: A system, method and computer program product are provided for programmable pixel processing in a computer graphics pipeline. In one embodiment of the present invention, arbitrary texture filtering is applied via a programmable shader.Type: GrantFiled: May 30, 2003Date of Patent: September 25, 2007Assignee: Nvidia CorporationInventors: Rui M. Bastos, Walter E. Donovan, Stephen D. Lew, Harold Robert Feldman Zatz, John Erik Lindholm
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Patent number: 7274369Abstract: Digital Image compositing using a programmable graphics processor is described. The programmable graphics processor supports high-precision data formats and can be programmed to complete a plurality of compositing operations in a single pass through a fragment processing pipeline within the programmable graphics processor. Source images for one or more compositing operations are stored in graphics memory, and a resulting composited image is output or stored in graphics memory. More-complex compositing operations, such as blur, warping, morphing, and the like, can be completed in multiple passes through the fragment processing pipeline. A composited image produced during a pass through the fragment processing pipeline is stored in graphics memory and is available as a source image for a subsequent pass.Type: GrantFiled: June 9, 2005Date of Patent: September 25, 2007Assignee: NVIDIA CorporationInventors: Rui M. Bastos, Daniel Elliott Wexler, Larry Gritz, Jonathan Rice, Harold Robert Feldman Zatz, Matthew N. Papakipos, David Kirk
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Patent number: 7154507Abstract: A system, method and computer program product are provided for texture shading in a hardware graphics processor. Initially, a plurality of texture coordinates is identified. Further, it is determined whether a hardware graphics processor is operating in a texture shader mode. If the hardware graphics processor is operating in the texture shader mode, the texture coordinates are mapped to colors utilizing a plurality of texture shader stages in the hardware graphics processor. If, however, the hardware graphics processor is not operating in the texture shader mode, the texture coordinates are mapped to colors utilizing a conventional graphics application program interface (API) in conjunction with the hardware graphics processor.Type: GrantFiled: September 15, 2004Date of Patent: December 26, 2006Assignee: NVIDIA CorporationInventors: Henry P. Moreton, John Erik Lindholm, Matthew N. Papakipos, Harold Robert Feldman Zatz
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Patent number: 7136070Abstract: A system, method and computer program product are provided for programmable pixel processing in a computer graphics pipeline. In one embodiment of the present invention, a computed arbitrary quantity is applied as texture address.Type: GrantFiled: May 23, 2003Date of Patent: November 14, 2006Assignee: NVIDIA CorporationInventors: Matthew N. Papakipos, Walter E. Donovan, Harold Robert Feldman Zatz, Henry Packard Moreton, John Erik Lindholm
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Patent number: 7109999Abstract: A method and system for implementing programmable texture lookups from texture coordinate sets. The method includes the step of generating a plurality of texture coordinates using a shader module. The shader module executes floating point calculations on received pixel data to generate the texture coordinates. A plurality of texture values are fetched using the texture coordinates. The fetching is performed by a texture unit coupled to receive the texture coordinates from the shader module. The fetching of the texture values is programmable with respect to the texture coordinates such that the number of texture coordinates are decoupled from the number of textures.Type: GrantFiled: May 29, 2003Date of Patent: September 19, 2006Assignee: nVidia CorporationInventors: John Erik Lindholm, Harold Robert Feldman Zatz, Walter E. Donovan, Matthew N. Papakipos
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Patent number: 7015913Abstract: A graphics processor and method for executing a graphics program as a plurality of threads where each sample to be processed by the program is assigned to a thread. Although threads share processing resources within the programmable graphics processor, the execution of each thread can proceed independent of any other threads. For example, instructions in a second thread are scheduled for execution while execution of instructions in a first thread are stalled waiting for source data. Consequently, a first received sample (assigned to the first thread) may be processed after a second received sample (assigned to the second thread). A benefit of independently executing each thread is improved performance because a stalled thread does not prevent the execution of other threads.Type: GrantFiled: June 27, 2003Date of Patent: March 21, 2006Assignee: NVIDIA CorporationInventors: John Erik Lindholm, Rui M. Bastos, Harold Robert Feldman Zatz
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Patent number: 6975321Abstract: A system and method are provided for generating multiple output packets in a single processing pass of a shader in a hardware graphics pipeline. Initially, graphics data is received, after which it is processed utilizing the shader of the hardware graphics pipeline to generate a plurality of output packets. The plurality of output packets is outputted from the shader of the hardware graphics pipeline in the single processing pass.Type: GrantFiled: May 5, 2003Date of Patent: December 13, 2005Assignee: NVIDIA CorporationInventors: John Erik Lindholm, Steven E. Molnar, Harold Robert Feldman Zatz
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Patent number: 6954204Abstract: A programmable graphics system and method for processing high precision graphics data represented in one or more data formats in one or more passes. Graphics program instructions executed by the system control the processing and format conversion of the data. The program instructions and the data are stored in a memory accessible by the system. Within the memory, contiguous memory entries can contain program instructions or data represented in different formats. The format used to represent a particular data element within the data, is specified in the state information maintained in the system and is used to configure format conversion units within the system. High precision data, such as floating color, is processed by the programmable graphics system and output via a digital to analog converter (DAC) for display.Type: GrantFiled: November 22, 2002Date of Patent: October 11, 2005Assignee: NVIDIA CorporationInventors: Harold Robert Feldman Zatz, Walter E. Donovan, John Erik Lindholm, Steven E. Molnar, John S. Montrym
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Patent number: 6870540Abstract: A system, method and computer program product are provided for programmable pixel processing in a computer graphics pipeline. Initially, pixel data is received from a source buffer. Thereafter, programmable operations are performed on the pixel data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register.Type: GrantFiled: June 19, 2001Date of Patent: March 22, 2005Assignee: NVIDIA CorporationInventors: John Erik Lindholm, Henry P. Moreton, Harold Robert Feldman Zatz
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Patent number: 6864893Abstract: A method and apparatus for generating depth values in a programmable graphics system. Depth values are calculated under control of a pixel program using a variety of sources as inputs to programmable computation units (PCUs) in the programmable graphics systems. The PCUs are used to compute traditional interpolated depth values and modified depth values. Th PCUs are also used to compute arbitrary depth values which, unlike traditional interpolated depth values and modified depth values, are not dependent on the coordinates of the geometry primitive with which the arbitrary depth values are associated. Several sources are available as inputs to the PCUs. Clipping with optional clamping is performed using either interpolated depth values or calculated depth values, where calculated depth values are arbitrary depth values or modified depth values. Final depth values, used for depth testing, are selected from interpolated depth values and arbitrary depth values after clipping is performed.Type: GrantFiled: November 22, 2002Date of Patent: March 8, 2005Assignee: NVIDIA CorporationInventor: Harold Robert Feldman Zatz
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Patent number: 6828980Abstract: A system, method and computer program product are provided for computer graphics processing. Initially, a height parameter is determined. Thereafter, a depth-direction component of the height parameter is calculated. A depth-value of a pixel is then modified utilizing the computed depth-direction component of the height parameter.Type: GrantFiled: January 10, 2003Date of Patent: December 7, 2004Assignee: NVIDIA CorporationInventors: Henry P. Moreton, John Erik Lindholm, Matthew N. Papakipos, Harold Robert Feldman Zatz
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Patent number: 6825843Abstract: A method and apparatus for executing loop and branch program instructions in a programmable graphics shader. The programmable graphics shader converts a sequence of instructions comprising a portion of a shader program and selects a first set of fragments to be processed. Subsequent sequences of instructions are converted until all of the instructions comprising the shader program have been executed on the first set of fragments. Each remaining set of fragments is processed by the shader program until all of the fragments are processed in the same manner. Furthermore, the instructions can contain one or more loop or branch program instructions that are conditionally executed. Additionally, when instructions within a loop as defined by a loop instruction are being executed a current loop count is pipelined through the programmable graphics shader and used as an index to access graphics memory.Type: GrantFiled: November 22, 2002Date of Patent: November 30, 2004Assignee: NVIDIA CorporationInventors: Roger L. Allen, Harold Robert Feldman Zatz