Patents by Inventor Harold Roberts

Harold Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12243712
    Abstract: Methods and systems for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area, based on an original set of exposure information. A pre-proximity effect correction (PEC) maximum dose for the local pattern density is determined, based on a pre-determined target post-PEC maximum dose. The pre-PEC maximum dose may be calculated near an edge of the desired shape. Methods also include modifying the original set of exposure information with the pre-PEC maximum dose to create a modified set of exposure information.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: March 4, 2025
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
  • Publication number: 20250028701
    Abstract: Self-Addressing Dynamic Random Access Memory (SADRAM) includes Dynamic Random Access Memory (DRAM) and a logic layer having direct access to the DRAM which provides symbolic addressing services. These services are provided by sequencers realized in the logic layer. The sequencers maintains a DRAM row or row-pair in sorted order, finds a location within the row or row-pair for a new data element, and inserts the new data element into the row or row-pair—all while preserving the sorted order. The sequencer is a plurality sequencer groups, each sequencer group is a plurality of sequencer cells. The sequencer cells to perform a highly parallel pipeline insertion of a new data element. The logic layer also defines a Self-Addressing Memory Central Processing Unit (SamPU) which is operatively coupled to the sequencer and configured to control the sequencer. The logic layer also provides program memory for SamPU and a memory cache in which is built an index database.
    Type: Application
    Filed: October 27, 2023
    Publication date: January 23, 2025
    Inventor: Harold Robert G. Trout
  • Publication number: 20240348332
    Abstract: Systems and techniques for laser transmitter characterization for accurate laser aging are described herein. A set of bias current-temperature pairs is collected for a laser diode. A bias current-temperature curve is calculated for the laser diode using the set of bias current-temperature pairs. A timestamp is assigned to the bias current-temperature curve. The bias current-temperature curve and the timestamp are stored in a non-volatile memory device communicatively coupled to a laser device that includes the laser diode. The bias current-temperature curve and the timestamp are transmitted to a cloud-based storage facility.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 17, 2024
    Inventors: Harold Roberts, Marta Seda, Pete Lee
  • Patent number: 12111764
    Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be coupled to a processor, which includes a memory controller. The memory controller may determine whether targeting of first data and second data by the processor to perform an operation results in processor-side cache misses. When targeting of the first data and the second data result in processor-side cache misses, the memory controller may determine a single memory access request that requests return of both the first data and the second data and instruct the processor to output the single memory access request to a memory system via one or more data buses coupled between the processor and the memory system to enable processing circuitry implemented in the processor to perform the operation based at least in part on the first data and the second data when returned from the memory system.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: October 8, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Harold Robert George Trout
  • Patent number: 12061554
    Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be communicative coupled to a processor via one or more data buses. Additionally, the memory system may include one or more memory devices that store data to be used by processing circuitry implemented in the processor to perform an operation. Furthermore, the memory system may include a memory controller that receives a memory access request that return of the data via the one or more data buses and, in response, determines a storage location of the data in the one or more memory devices based at least in part on the memory access request and instructs the memory system to store the data directly into a processor-side cache integrated with the processing circuitry to enable the processing circuitry implemented in the processor to perform the operation based on the data.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: August 13, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Harold Robert George Trout
  • Patent number: 11886166
    Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. The area comprises a plurality of pixels, and the original set of exposure information comprises dosages for the plurality of pixels in the area. A backscatter is calculated for a sub area of the area based on the original set of exposure information including the dosages for the plurality of pixels in the area. An increase in dosage for at least one pixel in a plurality of pixels in the sub area is determined, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: January 30, 2024
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
  • Patent number: 11836128
    Abstract: Dynamic Random Access Memory (DRAM) and a logic layer having direct access to the DRAM which provides symbolic addressing services. These services are provided by sequencers in the logic layer. The sequencers maintain a DRAM row or row-pair in sorted order, find a location and insert a new data element into the row or row-pair, all while preserving the sorted order. The sequencer is a plurality sequencer groups, each a plurality of sequencer cells. The sequencer cells perform a highly parallel pipeline insertion of a new data element. The logic layer also defines a Self-Addressing Memory Central Processing Unit (SamPU) operatively coupled to, and configured to control, the sequencer. The logic layer provides program memory for SamPU and a memory cache to build an index database. The database is subject to mitosis to accommodate the overflow of any item in the index database.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: December 5, 2023
    Assignee: SADRAM, INC.
    Inventor: Harold Robert G. Trout
  • Publication number: 20230386784
    Abstract: Methods and systems for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area, based on an original set of exposure information. A pre-proximity effect correction (PEC) maximum dose for the local pattern density is determined, based on a pre-determined target post-PEC maximum dose. The pre-PEC maximum dose may be calculated near an edge of the desired shape. Methods also include modifying the original set of exposure information with the pre-PEC maximum dose to create a modified set of exposure information.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 30, 2023
    Applicant: D2S, Inc.
    Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
  • Patent number: 11756765
    Abstract: Methods for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area of the desired shape based on an original set of exposure information. A backscatter for a sub area is calculated, based on the original set of exposure information. Dosage for at least one pixel in a plurality of pixels in the sub area is increased, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area. A pre-PEC maximum dose is determined for the local pattern density, based on a pre-determined target post-PEC maximum dose. The original set of exposure information is modified with the pre-PEC maximum dose and the increased dosage of the at least one pixel in the sub area to create a modified set of exposure information.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: September 12, 2023
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
  • Publication number: 20230205177
    Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. The area comprises a plurality of pixels, and the original set of exposure information comprises dosages for the plurality of pixels in the area. A backscatter is calculated for a sub area of the area based on the original set of exposure information including the dosages for the plurality of pixels in the area. An increase in dosage for at least one pixel in a plurality of pixels in the sub area is determined, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area.
    Type: Application
    Filed: February 14, 2023
    Publication date: June 29, 2023
    Applicant: D2S, Inc.
    Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
  • Publication number: 20230124768
    Abstract: Methods for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area, based on an original set of exposure information. A pre-proximity effect correction (PEC) maximum dose for the local pattern density is determined, based on a pre-determined target post-PEC maximum dose. The pre-PEC maximum dose is calculated near an edge of the desired shape. Methods also include modifying the original set of exposure information with the pre-PEC maximum dose to create a modified set of exposure information.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Applicant: D2S, Inc.
    Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
  • Patent number: 11604451
    Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. The area comprises a plurality of pixels, and the original set of exposure information comprises dosages for the plurality of pixels in the area. A backscatter is calculated for a sub area of the area based on the original set of exposure information. A dosage for at least one pixel in a plurality of pixels in the sub area is increased, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area. A modified set of exposure information is output, including the increased dosage of the at least one pixel in the sub area.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: March 14, 2023
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, Abhishek Shendre, William E. Guthrie, Ryan Pearman
  • Patent number: 11592802
    Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. A backscatter is calculated for the area of the pattern based on the exposure information. An artificial background dose is determined for the area. The artificial background dose comprises additional exposure information and is combined with the original set of exposure information creating a modified set of exposure information. A system for exposing a pattern in an area on a surface using a charged particle beam lithography is also disclosed.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: February 28, 2023
    Assignee: D2S, Inc.
    Inventors: Akira Fujimura, Harold Robert Zable, Nagesh Shirali, William E. Guthrie, Ryan Pearman
  • Publication number: 20220171711
    Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be communicative coupled to a processor via one or more data buses. Additionally, the memory system may include one or more memory devices that store data to be used by processing circuitry implemented in the processor to perform an operation. Furthermore, the memory system may include a memory controller that receives a memory access request that return of the data via the one or more data buses and, in response, determines a storage location of the data in the one or more memory devices based at least in part on the memory access request and instructs the memory system to store the data directly into a processor-side cache integrated with the processing circuitry to enable the processing circuitry implemented in the processor to perform the operation based on the data.
    Type: Application
    Filed: February 15, 2022
    Publication date: June 2, 2022
    Inventor: Harold Robert George Trout
  • Publication number: 20220171709
    Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be coupled to a processor, which includes a memory controller. The memory controller may determine whether targeting of first data and second data by the processor to perform an operation results in processor-side cache misses. When targeting of the first data and the second data result in processor-side cache misses, the memory controller may determine a single memory access request that requests return of both the first data and the second data and instruct the processor to output the single memory access request to a memory system via one or more data buses coupled between the processor and the memory system to enable processing circuitry implemented in the processor to perform the operation based at least in part on the first data and the second data when returned from the memory system.
    Type: Application
    Filed: February 15, 2022
    Publication date: June 2, 2022
    Inventor: Harold Robert George Trout
  • Patent number: 11281585
    Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be coupled to a processor, which includes a memory controller. The memory controller may determine whether targeting of first data and second data by the processor to perform an operation results in processor-side cache misses. When targeting of the first data and the second data result in processor-side cache misses, the memory controller may determine a single memory access request that requests return of both the first data and the second data and instruct the processor to output the single memory access request to a memory system via one or more data buses coupled between the processor and the memory system to enable processing circuitry implemented in the processor to perform the operation based at least in part on the first data and the second data when returned from the memory system.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Harold Robert George Trout
  • Patent number: 11281589
    Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be communicative coupled to a processor via one or more data buses. Additionally, the memory system may include one or more memory devices that store data to be used by processing circuitry implemented in the processor to perform an operation. Furthermore, the memory system may include a memory controller that receives a memory access request that requests return of the data via the one or more data buses and, in response, determines a storage location of the data in the one or more memory devices based at least in part on the memory access request and instructs the memory system to store the data directly into a processor-side cache integrated with the processing circuitry to enable the processing circuitry implemented in the processor to perform the operation based on the data.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Harold Robert George Trout
  • Publication number: 20210365204
    Abstract: The present disclosure includes systems, apparatuses and methods related to maintaining data in a sorted order in a memory array to improve access time to data in the memory array and directing access to a row of data in cache based upon an address associated with the data. In a number of embodiments, data can be sorted by receiving a portion of data for storage in a memory device, extracting a key associated with the portion of data, determining a row of an index table to store the key, and placing the key along with a number of keys in the row of the index table in a sorted order, wherein the sorted order is in relation to keys associated with portions of data previously stored in the memory device.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 25, 2021
    Inventors: Harold Robert G. Trout, Troy D. Larsen, Troy A. Manning, Timothy P. Finkbeiner, Glen E. Hush
  • Publication number: 20210365363
    Abstract: Methods, apparatuses, and systems related to mapping a virtual address using a physical address are described. In a memory system including a memory (e.g., cache) and a content addressable memory (CAM), the CAM can be configured to search data requested by a host from the memory based on multiple indicators stored in the CAM. For example, in the event that the data stored in the memory is not searchable based on a particular indicator such as a virtual address of a memory array (e.g., main memory), the CAM be configured to search the data based on another indicator such as a physical address of the memory array. Searching the data based on multiple indicators can resolve a synonym problem.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 25, 2021
    Inventors: Harold Robert G. Trout, Glen E. Hush, Troy A. Manning, Troy D. Larsen, Timothy P. Finkbeiner
  • Publication number: 20210365188
    Abstract: The present disclosure includes systems, apparatuses and methods related to maintaining data in a sorted order in a memory array to improve access time to data in the memory array and directing access to a row of data in cache based upon an address associated with the data. In a number of embodiments, data stored in tables in sorted order can allow access to data based on upon the keys and/or the sorted order of the data, which can increase access times to data the memory array.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 25, 2021
    Inventors: Harold Robert G. Trout, Glen E. Hush, Troy A. Manning, Timothy P. Finkbeiner, Troy D. Larsen