Patents by Inventor Harry Levinson
Harry Levinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9147653Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.Type: GrantFiled: October 14, 2014Date of Patent: September 29, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Lei Yuan, Jongwook Kye, Harry Levinson
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Publication number: 20150028489Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.Type: ApplicationFiled: October 14, 2014Publication date: January 29, 2015Inventors: Lei YUAN, Jongwook KYE, Harry LEVINSON
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Patent number: 8921225Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.Type: GrantFiled: February 13, 2013Date of Patent: December 30, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Lei Yuan, Jongwook Kye, Harry Levinson
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Patent number: 8843869Abstract: A method and apparatus for insertion of a via improving a manufacturability of a resulting device while ensuring compliance with DRC rules are disclosed. Embodiments include: determining a layer of a substrate of an IC design having a first via and a plurality of routes, the plurality of routes extending horizontally on the substrate and placed on one of a plurality of equally spaced vertical positions; comparing a region of the layer extending vertically between a first set of the plurality of routes and extending horizontally between a second set of the plurality of the routes with one or more threshold values, the region being adjacent to the first via and being separated from the plurality of routes; and inserting a second via based on the comparison.Type: GrantFiled: March 15, 2013Date of Patent: September 23, 2014Assignee: GlobalFoundries Inc.Inventors: Lei Yuan, Jongwook Kye, Harry Levinson
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Publication number: 20140282345Abstract: A method and apparatus for insertion of a via improving a manufacturability of a resulting device while ensuring compliance with DRC rules are disclosed. Embodiments include: determining a layer of a substrate of an IC design having a first via and a plurality of routes, the plurality of routes extending horizontally on the substrate and placed on one of a plurality of equally spaced vertical positions; comparing a region of the layer extending vertically between a first set of the plurality of routes and extending horizontally between a second set of the plurality of the routes with one or more threshold values, the region being adjacent to the first via and being separated from the plurality of routes; and inserting a second via based on the comparison.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Lei YUAN, Jongwook KYE, Harry LEVINSON
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Publication number: 20140225270Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.Type: ApplicationFiled: February 13, 2013Publication date: August 14, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Lei YUAN, Jongwook Kye, Harry Levinson
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Patent number: 8741763Abstract: An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.Type: GrantFiled: May 7, 2012Date of Patent: June 3, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Yuansheng Ma, Jongwook Kye, Harry Levinson, Hidekazu Yoshida, Mahbub Rashed
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Publication number: 20130292772Abstract: An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.Type: ApplicationFiled: May 7, 2012Publication date: November 7, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Yuansheng Ma, Jongwook KYE, Harry LEVINSON, Hidekazu YOSHIDA, Mahbub RASHED
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Publication number: 20090135390Abstract: Precise and repeatable alignment performance using asymmetric illumination is achieved by properly structuring, as by segmenting, an alignment mark on a reticle of a photolithographic exposure apparatus as a function of the type of asymmetric illumination, thereby improving resolution and repeatability of an alignment mark formed on a target substrate. Embodiments include double exposure techniques using dipole illumination with an angularly segmented alignment mark, e.g., at 45°, such that the first-order diffracted light is sent at 45° from the initial position of the dipole illumination.Type: ApplicationFiled: November 26, 2007Publication date: May 28, 2009Applicant: Advanced Micro Devices, Inc.Inventors: Bruno La Fontaine, Obert R. Wood, II, Harry Levinson
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Patent number: 7199994Abstract: For clamping a reticle within a lithography system, a first area in the center of the reticle is clamped to a chuck of the lithography system at a first time point. In addition, a second area toward an outer perimeter of the reticle is clamped to the chuck at a second time point after the first time point such that the reticle is flattened against the chuck. With such flattening of the reticle, image placement error on a semiconductor substrate is minimized.Type: GrantFiled: January 12, 2004Date of Patent: April 3, 2007Assignee: Advanced Micro Devices Inc.Inventors: Harry Levinson, Thomas White
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Patent number: 6872497Abstract: A methodology for forming a reflective mask is disclosed. The mask facilitates accurate pattern transfers as a substantially defect free reflective coating is formed therein. The mask can generally be formed according to four main steps, for example, which include depositing a reflective coating (e.g., formed of multiple layers) over a substrate, patterning and then inspecting for defects a masking material formed over the reflective coating, correcting such defects and finally patterning the reflective coating with the patterned masking material serving as a guide.Type: GrantFiled: February 4, 2003Date of Patent: March 29, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Harry Levinson, Bruno La Fontaine
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Method and apparatus for elimination of bubbles in immersion medium in immersion lithography systems
Publication number: 20050048223Abstract: A method of operating an immersion lithography system, including steps of immersing at least a portion of a wafer to be exposed in an immersion medium, wherein the immersion medium comprises at least one bubble; directing an ultrasonic wave through at least a portion of the immersion medium to disrupt and/or dissipate the at least one bubble; and exposing the wafer with an exposure pattern by passing electromagnetic radiation through the immersion medium subsequent to the directing. Also disclosed is a monitoring and control system for an immersion lithography system.Type: ApplicationFiled: September 2, 2003Publication date: March 3, 2005Inventors: Adam Pawloski, Amr Abdo, Gilles Amblard, Bruno LaFontaine, Ivan Lalovic, Harry Levinson, Jeffrey Schefske, Cyrus Tabery, Frank Tsai -
Publication number: 20050037269Abstract: A method of monitoring an immersion lithography system in which a wafer can be immersed in a liquid immersion medium for exposure by an exposure pattern. The method detects the presence of a foreign body in the immersion medium to thereby determine if the immersion medium in a state that is acceptable for exposing the wafer with the exposure pattern. Also disclosed is a monitoring and control system for an immersion lithography system.Type: ApplicationFiled: August 11, 2003Publication date: February 17, 2005Inventor: Harry Levinson
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Publication number: 20050018208Abstract: A method of monitoring an immersion lithography system in which a wafer can be immersed in a liquid immersion medium. The method detects an index of refraction of the immersion medium in a volume of the immersion medium through which an exposure pattern is configured to traverse and determines if the index of refraction is acceptable for exposing the wafer with the exposure pattern. Also disclosed is a monitoring and control system for an immersion lithography system.Type: ApplicationFiled: July 25, 2003Publication date: January 27, 2005Inventor: Harry Levinson
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Patent number: 6710853Abstract: An optical tool includes a tool body that is transparent to light. Pluralities of parallel opaque lines on the body form a first outline in the shape of the square, and a second outline in the shape of a square which is centrally located relative to and within the first-mentioned square. Each pair of adjacent parallel lines has therebetween a first region that allows transmission of light therethrough without changing phase thereof, and a second region alongside the first region that allows transmission of light therethrough while shifting the phase thereof by 90°. The phase shifting and non-phase shifting regions are positioned so that the images of the outlines provided by a lens on an object shit in position a substantial amount as the distance between the lens and the object is changed.Type: GrantFiled: August 31, 2001Date of Patent: March 23, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Bruno La Fontaine, Jongwook Kye, Harry Levinson
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Patent number: 6696847Abstract: In the present method of electrically testing the width of a line, a short pulse of laser energy is applied to the line to generate conductive electrons therein. An electrical potential is applied to the line to cause electrons to flow in the line, and current is measured to determine the width of the line.Type: GrantFiled: July 17, 2001Date of Patent: February 24, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Bruno M. LaFontaine, Jongwook Kye, Harry Levinson
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Patent number: 6535280Abstract: An optical monitor includes a body having a first plurality of parallel, substantially opaque, spaced apart lines thereon, and the second plurality of parallel, substantially opaque, spaced apart lines thereon, with a relatively small angle between the first and second pluralities of lines. A an image of the lines of the first plurality thereof is provided on the semiconductor body, upon relative movement of the monitor toward and away from the semiconductor body, the line images move relative to the semiconductor body. The images of the lines of the second plurality thereof provided on the semiconductor body move in a different manner upon relative movement if the monitor toward and away from the semiconductor body: The moiré fringe formed on the semiconductor body from images of the first and second plurality of lines during such movement is analyzed in order to achieve proper focus of the image on the semiconductor body.Type: GrantFiled: August 31, 2001Date of Patent: March 18, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Bruno La Fontaine, Jongwook Kye, Harry Levinson
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Patent number: 6515272Abstract: In an image monitoring apparatus, a pulsed-laser signal is modulated at a chosen frequency. The modulated signal is provided to an optical imaging system, the output signal is detected by an aerial image detector, and the signal from the aerial image detector is in turn amplified only at the chosen frequency. The apparatus includes an optical chopper for modulating the pulsed-laser signal, and a lock-in amplifier for amplifying the signal from the aerial image detector.Type: GrantFiled: September 29, 2000Date of Patent: February 4, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Bruno La Fontaine, Harry Levinson
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Patent number: 6399401Abstract: In a method of determining a linewidth of a polysilicon line formed by a lithographic process, a polysilicon layer is formed on a substrate. A line is patterned from said polysilicon layer using said lithographic process and a Van der Pauw structure is patterned from said polysilicon layer. N2 is then implanted into the polysilicon line and the polysilicon Van der Pauw structure to form a depletion barrier. A P-type dopant is the implanted into the polysilicon line and the polysilicon Van der Pauw structure and the dopant is activated. A sheet resistivity of the Van der Pauw structure is determined, and the linewidth of the polysilicon line is then determined by electrical linewidth measurement using the sheet resistivity of the Van der Pauw structure as the sheet resistivity of the polysilicon line. A related test structure is also disclosed.Type: GrantFiled: July 24, 2001Date of Patent: June 4, 2002Assignee: Advanced Micro Devices, In.Inventors: Jongwook Kye, Harry Levinson
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Patent number: 6208747Abstract: A method (300) of characterizing a lithographic scanning system includes the steps of printing a first pattern (302) using a reticle (220) having a first orientation with respect to the lithographic scanning system and measuring a critical dimension of the first pattern at a plurality of points (310). The method (300) further includes printing a second pattern (320) using the reticle (220) having a second orientation with respect to the lithographic scanning system different than the first orientation and measuring a critical dimension of the second pattern at the plurality of points (322).Type: GrantFiled: December 1, 1998Date of Patent: March 27, 2001Assignee: Advanced Micro Devices Inc.Inventors: Khanh B. Nguyen, Harry Levinson