Abstract: Devices and method for forming a shielding assembly including a first chip package structure sensitive to magnetic interference (MI), a second chip package structure sensitive to electromagnetic interference (EMI), and a shield surrounding sidewalls and top surfaces of the first chip package structure and the second chip package structure, in which the shield is a magnetic shielding material. In some embodiments, the shield may include silicon steel, in some embodiments, the shield may include Mu-metal. The silicon-steel-based or Mu-metal-based shield may provide both EMI and MI protection to multiple chip package structures with various susceptibilities to EMI and MI.

Abstract: The technologies described herein are generally directed to configuring carrier aggregation zones based on transmission information in a fifth generation (5G) network or other next generation networks. For example, a method described herein can include identifying, by carrier aggregation equipment including a processor, carrier transmission information corresponding to a first carrier signal and a second carrier signal. The method can further include analyzing, by the carrier aggregation equipment, the carrier transmission information to determine first overlap zone information representative of a first carrier overlap zone for the first carrier signal and the second carrier signal. Further, based on the first overlap zone information, the method includes facilitating configuring transmission parameter information representative of a transmission parameter applicable to transmission of the first carrier signal, to enable carrier aggregation by network equipment within the first carrier overlap zone.

Abstract: The subject technology selects a most recently created file from a set of files stored in a source table. The subject technology iterates, in the source table, starting from the most recently created file up to an age threshold to select a first set of files for performing a first defragmentation process. The subject technology sets an indication corresponding to a particular file that is a last file, from the first set of files, that meets the age threshold. The subject technology performs the first defragmentation process on the selected first set of files. The subject technology determines that the first defragmentation process was successful.

Abstract: The technologies described herein are generally directed to launching radio spectrum resources in a fifth generation (5G) network or other next generation networks. For example, a method described herein can include, confirming, by site launching equipment, installation of components of a base station, resulting in a confirmed installation. The method can further comprise, based on the confirmed installation, facilitating, by the site launching equipment, integrating the base station into a communications network. Further, in response to the integrating, launching, by the site launching equipment, operation of the base station for a testing of performance of the base station, the testing resulting in a tested base station. The method can further comprise activating, by the site launching equipment, the tested base station for use by authorized user equipment via the communications network.

Abstract: The technologies described herein are generally directed to configuring carrier aggregation zones based on transmission information in a fifth generation (5G) network or other next generation networks. For example, a method described herein can include identifying, by carrier aggregation equipment including a processor, carrier transmission information corresponding to a first carrier signal and a second carrier signal. The method can further include analyzing, by the carrier aggregation equipment, the carrier transmission information to determine first overlap zone information representative of a first carrier overlap zone for the first carrier signal and the second carrier signal. Further, based on the first overlap zone information, the method includes facilitating configuring transmission parameter information representative of a transmission parameter applicable to transmission of the first carrier signal, to enable carrier aggregation by network equipment within the first carrier overlap zone.

Abstract: Three dimensional cross-point array memory devices and selecting cells within a three dimensional cross-point array memory. In a particular embodiment, three different voltages levels are applied to bit lines of the cross point array to allow for selection of a specific cell. Series of select devices may be implemented to provide a high voltage and a low voltage to specific bit lines, while a middle voltage may also be provided. In a particular embodiment, the select devices comprise Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs).

Abstract: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.

Abstract: Magnetic shift registers in which data writing and reading is accomplished by moving the magnetic domain walls by electric current. Various embodiments of domain wall nodes or anchors that stabilize a domain wall are provided. In some embodiments, the wall anchors are elements separate from the magnetic track. In other embodiments, the wall anchors are disturbances in the physical configuration of the magnetic track. In still other embodiments, the wall anchors are disturbances in the material of the magnetic track.

Abstract: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.

Abstract: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.

Abstract: The disclosure is related to three dimensional cross-point array memory devices and selecting cells within a three dimensional cross-point array memory. In a particular embodiment, three different voltages levels are applied to bit lines of the cross point array to allow for selection of a specific cell. Series of select devices may be implemented to provide a high voltage and a low voltage to specific bit lines, while a middle voltage may also be provided. In a particular embodiment, the select devices comprise Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs).

Abstract: A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.

Abstract: Magnetic shift registers in which data writing and reading is accomplished by moving the magnetic domain walls by electric current. Various embodiments of domain wall nodes or anchors that stabilize a domain wall are provided. In some embodiments, the wall anchors are elements separate from the magnetic track. In other embodiments, the wall anchors are disturbances in the physical configuration of the magnetic track. In still other embodiments, the wall anchors are disturbances in the material of the magnetic track.

Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.

Abstract: A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.

Abstract: A pseudo-spin valve for memory applications, such as magnetoresistive random access memory (MRAM), and methods for fabricating the same, are disclosed. Advantageously, memory devices with the advantageous pseudo-spin valve configuration can be fabricated without cobalt-iron and without anti-ferromagnetic layers, thereby promoting switching repeatability.

Abstract: A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.

Abstract: A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM cell. The critical areas of the delays may be positioned so that a common line of sight cannot be made between each delay and a circuit node.

Abstract: A method and system is disclosed for preventing write errors in a Single Event Upset (SEU) hardened static random access memory (SRAM) cell. A compensating element has been connected to a feedback path of the SRAM cell. The compensating element operates to cancel out capacitive coupling generated in an active delay element of the SRAM cell. If the compensating element sufficiently cancels the effects of the capacitive coupling, a write error will not occur in the SRAM cell. The compensating element also occupies a smaller silicon area than other proposed solutions.

Abstract: A method and system is disclosed for reducing proton and heavy ion SEU sensitivity of a static random access memory (SRAM) cell. A first passive delay element has been inserted in series with an active delay element in a first feedback path of the SRAM cell, and a second passive delay element has been inserted in a second feedback path of the SRAM cell. The passive delay elements reduce the proton SEU sensitivity of the SRAM cell, and the active delay element reduces the heavy ion sensitivity of the SRAM cell. The passive delay elements also protect the SRAM cell against SEUs that may occur when the SRAM cell is in dynamic mode.