Patents by Inventor Harry Liu

Harry Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MRAM architectures for increased write selectivity
    Patent number: 6522574
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: February 18, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • MRAM architecture using offset bits for increased write selectivity
    Patent number: 6424561
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: July 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • MRAM architectures for increased write selectivity
    Patent number: 6424564
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: July 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • Passivated magneto-resistive bit structure
    Publication number: 20020085412
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Application
    Filed: February 14, 2002
    Publication date: July 4, 2002
    Inventors: Harry Liu, Lonny Berg, William L. Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • Passivated magneto-resistive bit structure and passivation method therefor
    Publication number: 20020080645
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Application
    Filed: January 24, 2002
    Publication date: June 27, 2002
    Applicant: Micron Technology, Inc.
    Inventors: Harry Liu, Lonny Berg, William L. Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • Passivated magneto-resistive bit structure and passivation method therefor
    Patent number: 6392922
    Abstract: A passivated magneto-resistive bit structure is disclosed in which surfaces subject to oxidation or corrosion are protected. In one embodiment a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: May 21, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Harry Liu, Lonny Berg, William L. Larson, Shaoping Li, Theodore Zhu, Joel Drewes
  • MRAM architectures for increased write selectivity
    Publication number: 20020012268
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Application
    Filed: September 26, 2001
    Publication date: January 31, 2002
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu
  • MRAM architectures for increased write selectivity
    Publication number: 20020012269
    Abstract: MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.
    Type: Application
    Filed: September 25, 2001
    Publication date: January 31, 2002
    Inventors: Shaoping Li, Theodore Zhu, Anthony S. Arrott, Harry Liu, William L. Larson, Yong Lu