Patents by Inventor Harry M. Yudenfriend

Harry M. Yudenfriend has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10592129
    Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices by a host accessing logical devices provisioned with a capacity from physical devices managed by a control unit. The host establishes with the control unit an association of logical devices and alias addresses assigned to the logical devices, wherein the alias addresses are associated with an alias management group. Alias address pool information is generated indicating each of the logical devices and their assigned alias addresses indicated in the association. The host uses from the alias address pool information any one of the alias addresses in the alias address pool information to access any of the logical devices associated with the same alias management group as the alias address.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Susan K. Candelaria, Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Matthew J. Kalos, Dale F. Riedy, Richard A. Ripberger, Harry M. Yudenfriend
  • Patent number: 10585821
    Abstract: Aspects include sending a request to perform a unit of work that includes a synchronous I/O operation. The sending is from an operating system (OS) executing on a server to firmware located on the server. The synchronous I/O request includes a command request block that includes an operation code identifying the synchronous I/O operation and a identifier of a persistent storage control unit (SCU). The OS waits for the synchronous I/O to complete and the unit of work remains active during the waiting. The firmware detects that the synchronous I/O operation has completed. A command response block that includes completion status information about the synchronous I/O operation is received by the OS from the firmware. The unit of work is completed in response to the I/O operation completing.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Beth A. Glendening, Dale F. Riedy, Harry M. Yudenfriend
  • Patent number: 10579287
    Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices by a host accessing logical devices provisioned with a capacity from physical devices managed by a control unit. The host establishes with the control unit an association of logical devices and alias addresses assigned to the logical devices, wherein the alias addresses are associated with an alias management group. Alias address pool information is generated indicating each of the logical devices and their assigned alias addresses indicated in the association. The host uses from the alias address pool information any one of the alias addresses in the alias address pool information to access any of the logical devices associated with the same alias management group as the alias address.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Susan K. Candelaria, Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Matthew J. Kalos, Dale F. Riedy, Richard A. Ripberger, Harry M. Yudenfriend
  • Publication number: 20200042453
    Abstract: Provided are a computer program product, system, and method for managing access requests from a host to tracks in storage. A cursor is set to point to a track in a range of tracks established for sequential accesses. Cache resources are accessed for the cache for tracks in the range of tracks in advance of processing access requests to the range of tracks. Indication is received of a subset of tracks in the range of tracks for subsequent access transactions and a determination is made whether the cursor points to a track in the subset of tracks. The cursor is set to point to a track in the subset of tracks and cache resources are accessed for tracks in the subset of tracks for anticipation of access transactions to tracks in the subset of tracks.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 6, 2020
    Inventors: Ronald E. Bretschneider, Susan K. Candelaria, Beth A. Peterson, Dale F. Riedy, Peter G. Sutton, Harry M. Yudenfriend
  • Patent number: 10528474
    Abstract: Provided are a computer program product, system, and method for managing access requests from a host to tracks in storage. A cursor is set to point to a track in a range of tracks established for sequential accesses. Cache resources are accessed for the cache for tracks in the range of tracks in advance of processing access requests to the range of tracks. Indication is received of a subset of tracks in the range of tracks for subsequent access transactions and a determination is made whether the cursor points to a track in the subset of tracks. The cursor is set to point to a track in the subset of tracks and cache resources are accessed for tracks in the subset of tracks for anticipation of access transactions to tracks in the subset of tracks.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ronald E. Bretschneider, Susan K. Candelaria, Beth A. Peterson, Dale F. Riedy, Peter G. Sutton, Harry M. Yudenfriend
  • Publication number: 20190332270
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Application
    Filed: July 10, 2019
    Publication date: October 31, 2019
    Inventors: Peter D. Driever, Charles W. Gainey, JR., Steven G. Glassen, Thomas B. Mathias, Kenneth J. Oakes, Peter G. Sutton, Peter K. Szwed, Elpida Tzortzatos, Harry M. Yudenfriend
  • Patent number: 10437730
    Abstract: A method for synchronizing primary and secondary read cache in a data replication environment is disclosed. In one embodiment, such a method includes monitoring contents of a primary read cache at a primary site. The method periodically sends, from the primary site to a secondary site, information regarding the contents of the primary read cache, such as a list of storage elements cached in the primary read cache. In certain embodiments, the information also includes temperature information indicating how frequently the storage elements are accessed. The method uses, at the secondary site, the information to substantially synchronize a secondary read cache with the primary read cache. A corresponding system and computer program product are also disclosed herein.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Kalos, Peter G. Sutton, Harry M. Yudenfriend
  • Publication number: 20190303015
    Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices for a control unit managing access by hosts to logical devices configured with capacity from attached physical devices. An alias management group of logical devices and alias addresses assigned to the logical devices is configured. A plurality of requests to establish an association of the host with a logical device and the alias addresses assigned to the logical devices in the alias management group are received from a host. Acknowledgment is made to the host that the association is established in response to determining that the host is assigned the logical devices and alias addresses of the logical devices in the alias management group. The host can use one available alias address assigned to any one of the logical devices to access any one of the logical devices indicated in the association.
    Type: Application
    Filed: June 19, 2019
    Publication date: October 3, 2019
    Inventors: Susan K. Candelaria, Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Matthew J. Kalos, Dale F. Riedy, Richard A. Ripberger, Harry M. Yudenfriend
  • Publication number: 20190286344
    Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices by a host accessing logical devices provisioned with a capacity from physical devices managed by a control unit. The host establishes with the control unit an association of logical devices and alias addresses assigned to the logical devices, wherein the alias addresses are associated with an alias management group. Alias address pool information is generated indicating each of the logical devices and their assigned alias addresses indicated in the association. The host uses from the alias address pool information any one of the alias addresses in the alias address pool information to access any of the logical devices associated with the same alias management group as the alias address.
    Type: Application
    Filed: May 31, 2019
    Publication date: September 19, 2019
    Inventors: Susan K. Candelaria, Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Matthew J. Kalos, Dale F. Riedy, Richard A. Ripberger, Harry M. Yudenfriend
  • Patent number: 10402123
    Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices for a control unit managing access by hosts to logical devices configured with capacity from attached physical devices. An alias management group of logical devices and alias addresses assigned to the logical devices is configured. A plurality of requests to establish an association of the host with a logical device and the alias addresses assigned to the logical devices in the alias management group are received from a host. Acknowledgment is made to the host that the association is established in response to determining that the host is assigned the logical devices and alias addresses of the logical devices in the alias management group. The host can use one available alias address assigned to any one of the logical devices to access any one of the logical devices indicated in the association.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: September 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Susan K. Candelaria, Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Matthew J. Kalos, Dale F. Riedy, Richard A. Ripberger, Harry M. Yudenfriend
  • Patent number: 10387040
    Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter D. Driever, Charles W. Gainey, Jr., Steven G. Glassen, Thomas B. Mathias, Kenneth J. Oakes, Peter G. Sutton, Peter K. Szwed, Elpida Tzortzatos, Harry M Yudenfriend
  • Publication number: 20190179782
    Abstract: Provided are a computer program product, system, and method for non-disruptive encoding of source data in a source data set migrated to a target data set. The source data in the source data set is migrated to a target data set by encoding the source data to produce encoded source data to copy to a target data set. In response to receiving write data for the source data set, the write data is encoded to produce encoded write data to copy to the target data set. Input/Output (“I/O”) requests to the source data set are redirected to the target data set having encoded data for the source data set.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 13, 2019
    Inventors: John H. Hogan, Richard G. Pace, Harry M. Yudenfriend
  • Publication number: 20190163576
    Abstract: One general aspect of device reservation management in accordance with the present description, is directed to a host issuing I/O data requests to a primary device which synchronously mirrors data to a secondary data storage device wherein both devices are reserved for exclusive use by the host for I/O data requests. In response to a loss of communication connectivity on all paths to the primary storage controller controlling the primary device, the host confirms whether a communication path to the primary device has been established and whether the primary device remains reserved to the host. Upon successful confirmations, the reservation of the primary device is repaired such that I/O data requests to the reserved primary device continue. Other features and aspects may be realized, depending upon the particular application.
    Type: Application
    Filed: November 30, 2017
    Publication date: May 30, 2019
    Inventors: Scott B. Compton, Matthew R. Craig, Clint A. Hardy, Tri M. Hoang, Matthew J. Kalos, John G. Thompson, Harry M. Yudenfriend
  • Publication number: 20190140968
    Abstract: A first device determines whether an indicator is configured to allow use of an increased value for an information unit pacing credit that is greater than a default value for the information unit pacing credit, where the information unit pacing credit indicates a number of information units that a second device is allowed to send to the first device without waiting for any additional response from the first device. In response to determining that the indicator is configured to allow use of the increased value for the information unit pacing credit that is greater than the default value for the information unit pacing credit, the first device adjusts the information unit pacing credit via a response sent from the first device to the second device, to the increased value that is greater than the default value.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 9, 2019
    Inventors: Roger G. Hathorn, Bret W. Holley, Harry M. Yudenfriend
  • Patent number: 10250516
    Abstract: A first device determines whether an indicator is configured to allow use of an increased value for an information unit pacing credit that is greater than a default value for the information unit pacing credit, where the information unit pacing credit indicates a number of information units that a second device is allowed to send to the first device without waiting for any additional response from the first device. In response to determining that the indicator is configured to allow use of the increased value for the information unit pacing credit that is greater than the default value for the information unit pacing credit, the first device adjusts the information unit pacing credit via a response sent from the first device to the second device, to the increased value that is greater than the default value.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Roger G. Hathorn, Bret W. Holley, Harry M. Yudenfriend
  • Publication number: 20190089649
    Abstract: Provided are a computer program product, system, and method for resource allocation in accordance with one embodiment of the present description, in which a resource allocation such as a buffer credit allocation for a port in a storage area network is initialized as a function of a measurement of a length of a communication link for the port of the storage area network. In one embodiment, the length measurement is a function of a minimum command response time of a command issued over the communication link. Other aspects of resource allocation in accordance with the present description are described.
    Type: Application
    Filed: October 16, 2018
    Publication date: March 21, 2019
    Inventors: Roger G. Hathorn, Dale F. Riedy, Harry M. Yudenfriend
  • Publication number: 20190073310
    Abstract: Provided are a computer program product, system, and method for managing access requests from a host to tracks in storage. A cursor is set to point to a track in a range of tracks established for sequential accesses. Cache resources are accessed for the cache for tracks in the range of tracks in advance of processing access requests to the range of tracks. Indication is received of a subset of tracks in the range of tracks for subsequent access transactions and a determination is made whether the cursor points to a track in the subset of tracks. The cursor is set to point to a track in the subset of tracks and cache resources are accessed for tracks in the subset of tracks for anticipation of access transactions to tracks in the subset of tracks.
    Type: Application
    Filed: September 6, 2017
    Publication date: March 7, 2019
    Inventors: Ronald E. Bretschneider, Susan K. Candelaria, Beth A. Peterson, Dale F. Riedy, Peter G. Sutton, Harry M. Yudenfriend
  • Patent number: 10216641
    Abstract: Aspects include a computer-implemented method for managing alias devices across logical control units. Aspects include establishing one or more alias management groups associated with a set of one or more logical control units. Aspects also include responsive to one or more changes to the set of network paths of a first logical control unit in the set of logical control units performing a method comprising: marking a first alias management group associated with the first logical control unit as invalid for alias borrowing. Then, performing a first synchronized CPU enablement operation that ensures each of the plurality of CPUs has enabled. Aspects include determining whether a second alias management group exists having a second set of control units that matches the set of paths of the first control unit and associating the first control unit with the second alias management group.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS SYSTEMS CORPORATION
    Inventors: Scott B. Compton, Tri M. Hoang, Stephen M. Kocik, Dale F. Riedy, Harry M. Yudenfriend
  • Patent number: 10218507
    Abstract: Aspects include providing automatic access control and security for a synchronous input/output (I/O) link. Providing automatic access control and security includes initializing devices of a storage environment over a first link to verify that the devices are available within the storage environment; building a table of identifiers, where each of the identifiers is assigned one of the devices that have been initialized; and verifying a first device attempting to perform synchronous I/O commands across the synchronization I/O link by confirming that an identifier assigned to the first device is within the table of identifiers.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David F. Craddock, Beth A. Glendening, Dale F. Riedy, Peter G. Sutton, Harry M. Yudenfriend
  • Publication number: 20190034366
    Abstract: Aspects include sending a request to perform a unit of work that includes a synchronous I/O operation. The sending is from an operating system (OS) executing on a server to firmware located on the server. The synchronous I/O request includes a command request block that includes an operation code identifying the synchronous I/O operation and a identifier of a persistent storage control unit (SCU). The OS waits for the synchronous I/O to complete and the unit of work remains active during the waiting. The firmware detects that the synchronous I/O operation has completed. A command response block that includes completion status information about the synchronous I/O operation is received by the OS from the firmware. The unit of work is completed in response to the I/O operation completing.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Inventors: David F. Craddock, Beth A. Glendening, Dale F. Riedy, Harry M. Yudenfriend