Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure.

Abstract: A method for making contact to a narrow width PN junction region in any desired semiconductor body is described. A substantially vertical conformal conductive layer is formed over the desired PN junction region. The body is heated at a suitable temperature to cause a dopant to diffuse from the vertical conductive layer into the semiconductor body to form the narrow width PN junction region. A substantially horizontal conductive layer makes contact to the substantially vertical layer so as to have the horizontal conductive layer in electrical contact to the PN junction region. Electrical contact can be made to the horizontal conductive layer at any convenient location. A lateral PNP transistor is one type of very small device that can be made using the method of the present invention.

Abstract: A high sheet resistivity, doped semiconductor resistor is made by a process which produces a resistor diffusion or ion implantation mask having a narrow dimension determined by a "sidewall" technique. The sidewall technique defines the narrow dimension by the thickness of a doped or undoped layer deposited on a different underlying layer having horizontal and vertical surfaces. The horizontal portion of the deposited layer is removed by anistropic etching to leave only the vertical portion. The vertical portion, if undoped, is removed to define a diffused or ion-implanted resistor. The vertical portion, if doped, optionally may be removed, after heating to form a diffused resistor, or may be left in place to form a resistor in shunt with the diffused resistor.

Abstract: A dynamic memory cell has a P+ injector region surrounded by an N+ region in an N- layer on an N+ layer. The injector region is placed between N+ source and drain regions. Holes injected into the N-layer are trapped by the high-low junctions at the N+, N- interfaces and are detected by sensing the source-drain current. Current levels are used to establish binary one and zero levels in the cell. Four masks in an aligned procedure simplify fabrication.

Abstract: A dynamic memory cell uses a low barrier Schottky contact at a drain region to eliminate the need for an external gating diode. The drain is separated from source and injector regions by a heavily doped N+ reach through region extending to a heavily doped N+ blanket semiconductor. Holes injected into one of the separated regions are trapped by high-low junctions and are detected by sensing the source-drain current.

Abstract: A method for eliminating deposited residues, for example polysilicon residue, on vertical silicon dioxide sidewalls that have been reactive ion etched includes reshaping the sidewalls to have a slope of at least +30.degree. relative to the vertical direction of the sidewall.

Abstract: The present invention provides a method for planarizing a non-uniform thickness of oxide, for example silicon dioxide as is formed over oxide-filled trenches used in deep dielectric isolation in integrated circuits. The oxide is removed by a planarizing resist-etching process so that etching in thicker resist areas proceeds at a rate slower than etching in thinner resist areas. A referred etchant is HF gas and etching is preferably at an elevated temperature.

Abstract: A method for making lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages. The lateral PNP or NPN device resulting from the method is in a monocrystalline silicon pocket wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline silicon region. The P emitter or N emitter diffusion is located over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket.

Abstract: A method for making a high performance bipolar transistor characterized by self-aligned emitter and base regions and minimized base and emitter contact spacing. The disclosed method comprises forming a recessed oxide-isolated structure having opposite conductivity epitaxial layer and substrate. Multiple layered mass of alternating silicon nitride and silicon dioxide layers are placed over the base region and over the collector reach-through region. Polycrystalline silicon is deposited between the mesas. The mesas are undercut-etched to expose the extrinsic base region which is ion implanted. Then, the mesas are removed to expose the emitter and intrinsic base regions as well as the collector reach-through regions. The latter exposed regions are ion implanted appropriately. Contacts are made directly to the emitter and collector reach-through regions and indirectly via the polysilicon to the base region.

Abstract: A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions.

Abstract: A method is given for fabricating vertical NPN and PNP structures on the same semiconductor body. The method involves providing a monocrystalline semiconductor substrate having regions of monocrystalline silicon isolated from one another by isolation regions. Buried regions are formed overlapping the juncture of the substrate and epitaxial layer and are located in at least one of the regions of isolated monocrystalline silicon. The P base region in the NPN designated regions and a P reach-through in the PNP designated regions are formed simultaneously. The emitter region in the NPN regions and base contact region in the PNP regions are then formed simultaneously. The P emitter region in the PNP regions is then implanted by suitable ion implantation techniques. A Schottky Barrier collector contact in the PNP regions are formed. Electrical contacts are then made to the PNP and NPN transistor elements. A PNP device may be fabricated without the formation of an NPN device if it is so desired.

Abstract: Lateral PNP or NPN devices in isolated monocrystalline silicon pockets wherein silicon dioxide isolation surrounds the pocket and partially, below the surface, within the isolated monocrystalline region are described. The P emitter or N emitter diffusion is made over the portion of the silicon dioxide that partially extends into the monocrystalline isolated pocket. This structure reduces the vertical current injection which will give relatively high (beta) gain even at low base to emitter voltages.

Abstract: A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions.

Abstract: A method is given for fabricating vertical NPN and PNP structures on the same semiconductor body. The method involves providing a monocrystalline semiconductor substrate having regions of monocrystalline silicon isolated from one another by isolation regions. Buried regions are formed overlapping the juncture of the substrate and epitaxial layer and are located in at least one of the regions of isolated monocrystalline silicon. The P base region in the NPN designated regions and a P reach-through in the PNP designated regions are formed simultaneously. The emitter region in the NPN regions and base contact region in the PNP regions are then formed simultaneously. The P emitter region in the PNP regions is then implanted by suitable ion implantation techniques. A Schottky Barrier collector contact in the PNP regions are formed. Electrical contacts are then made to the PNP and NPN transistor elements. A PNP device may be fabricated without the formation of an NPN device if it is so desired.

Abstract: Excessive leakage after initial forward stress, exhibited by subsequently reverse stressed nitride defined, Schottky barrier diodes is solved by the elimination of the "mouse hole" or undercut cavity in the oxide layer beneath the nitride ring defining the Schottky contact to the underlying silicon. The aforementioned cavity is filled by depositing chemical vapor deposited (CVD) oxide onto the nitride layer, into the nitride ring and the undercut oxide cavity beneath the ring and onto the underlying silicon substrate exposed through the nitride ring. The CVD oxide is then reactively ion etched to remove it except along the vertical walls of the nitride ring and the oxide cavity. The Schottky metal is deposited on the silicon substrate exposed by the reactive ion etching step.