Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

Abstract: A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.

Abstract: A system and method are provided for capturing a high resolution, high frame rate video using a Universal Serial Bus (USB) port. Generally, the method involves transmitting a High-Definition Multimedia Interface (HDMI) video including a number of video frames from a HDMI-source. Receiving the HDMI video and buffering and splitting each one of the video frames into a plurality of split video frames. Each of the split video frames is converted into a number of USB data packets. USB data packets from each of the split video frames are then interleaved to form a stream of USB data packets. The stream of USB data packets is coupled to a host system, which executes a program to stitch the USB data packets back together to reassemble each of the video frames, and order the video frames to restore or recreate the HDMI video.

Abstract: A memory array includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports a first operating mode where only one word line in the memory array is actuated during memory access and a second operating mode where one word line per sub-array is simultaneously actuated during an in-memory computation performed as a function of weight data stored in the memory and applied feature data. Computation circuitry coupling each memory cell to the local bit line for each column of the sub-array logically combines a bit of feature data for the in-memory computation with a bit of weight data to generate a logical output on the local bit line which is charge shared with the global bit line.

Abstract: A differential video rendering system, including a graphics processing unit (GPU); a graphical display coupled to the GPU; a video decoder configured to decode a bitstream of encoded data into a plurality of sets of decoded blocks; at least one processor configured to: generate, based on a first set of the plurality of sets of decoded blocks, a first differential video frame comprising a plurality of sets of differential regions, normalize each set of the plurality of sets of differential regions to a fixed size block to provide a normalized plurality of sets of differential regions, map a respective set of the normalized plurality of sets of differential regions to align with a respective tile size region of a plurality of tile size regions conforming with the GPU, generate a hierarchal region tree based on the normalized plurality of sets of differential regions mapped to the plurality of tile size regions, and generate a plurality of optimal regions based on the hierarchal region tree satisfying a predefin

Abstract: One example includes a method for measuring a quiescent current in a switching voltage regulator. The method includes generating a mathematical model of a circuit design associated with the switching voltage regulator. The mathematical model includes measurable parameters to describe a switching current of a power switch of the switching voltage regulator. The method also includes fabricating a circuit comprising the switching voltage regulator based on the circuit design. The fabricated circuit includes the power switch and conductive I/O. The method also includes coupling the conductive I/O of the fabricated circuit to a circuit test fixture and providing electrical signals to the conductive I/O via the circuit test fixture. The method also includes measuring the measurable parameters in response to the electrical signals and applying the measurable parameters to the mathematical model to calculate the switching current.

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

Abstract: An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.

Abstract: A computer-implemented method, computer-readable medium and computer system to execute containerized applications includes initiating a Supervisor Cluster on top of a SDDC to support execution of containerized applications. A supervisor cluster namespace is created on the Supervisor Cluster. A storage policy is attached to the supervisor cluster namespace. Then, a control plane is bootstrapped, and containerized applications are executed in a virtual machine cluster using vSphere pods as the worker nodes in the virtual machine cluster.

Abstract: An example method of configuring a cluster network for an application management system having virtual machines (VMs) executing on a virtualization layer in a cluster of hosts connected to a physical network, wherein the application management system is integrated with the virtualization layer, the method including: deploying, by a virtualization management server, a master server of the application management system prior to configuration of a cluster network that connects the VMs, the master server connected to the virtualization management server by a management network isolated from the cluster network; configuring, by the master server in cooperation with a network manager, the cluster network to connect the VMs; and connecting, by the master server in cooperation with the network manager, the cluster network to an edge node configured to support external ingress/egress for the cluster network.

Abstract: An electrical apparatus includes: a first electrically conductive contact; and a switch. The switch includes: an electrically conductive moveable contact; a cam; an actuator connected to the electrically conductive moveable contact, the actuator including a cam region configured to interact with the cam. Rotation of the cam moves the actuator between one of two stable positions, the two stable positions including a first position and a second position. The switch also includes an elastic assembly coupled to the actuator, the elastic assembly configured to hold the actuator in either of the two stable positions. When the actuator is in the first position, the switch is closed and the electrically conductive moveable contact is connected to the first electrically conductive contact; and, when the actuator is in the second position, the switch is open and the electrically conductive moveable contact is separated from the first electrically conductive contact.

Abstract: A method comprises creating an electronic module design having a plurality of electronic components comprising a plurality of low power enabled components and defining a model of functional behavior and of power behavior. The method also comprises identifying sequential element information correlated with an electronic component based on the models of functional and power behavior. the sequential element information comprising a first control signal and a second control signal. A coverage test is generated based on the sequential element information and is configured to quantify behavior of the electronic component based on a relationship of a plurality of activation states of a first control signal to a plurality of activation states of a second control signal. A simulation file is run to simulate operation of the electronic module design, and a performance status of the electronic module design is determined in response to running the simulation file.

Abstract: Container images are fetched in a clustered container host system with a shared storage device. Fetching a first container image in a first virtual machine includes creating a first virtual disk in the shared storage device, storing an image of the first container in the first virtual disk, mounting the first virtual disk to the first virtual machine, and updating a metadata cache to associate the image of the first container to the first virtual disk. Fetching a second container image in a second virtual machine includes checking the metadata cache to determine that a portion of the image of the second container is stored in the first virtual disk, creating a second virtual disk in the shared storage device, adding a reference to the first virtual disk in a metadata of the second virtual disk, and mounting the second virtual disk to the second virtual machine.

Abstract: A device may process data associated with a first entity and a second entity, using one or more machine learning techniques, to identify a set of trends associated with a set of documents. The device may receive new documents associated with the first entity and the second entity. The device may generate, based on the set of trends, a first set of exceptions indicating that a new document is associated with a first type of error. The device may generate, using a similarity analysis technique, a second set of exceptions indicating that a new document is associated with a second type of error. The device may communicate with one or more systems to perform one or more actions associated with correction or prevention of processing errors relating to the new document based a claim relating to the first set of exceptions or the second set of exceptions.

Abstract: Container images are fetched in a clustered container host system with a shared storage device. Fetching a first container image in a first virtual machine includes creating a first virtual disk in the shared storage device, storing an image of the first container in the first virtual disk, mounting the first virtual disk to the first virtual machine, and updating a metadata cache to associate the image of the first container to the first virtual disk. Fetching a second container image in a second virtual machine includes checking the metadata cache to determine that a portion of the image of the second container is stored in the first virtual disk, creating a second virtual disk in the shared storage device, adding a reference to the first virtual disk in a metadata of the second virtual disk, and mounting the second virtual disk to the second virtual machine.

Abstract: Container images are fetched in a clustered container host system with a shared storage device. Fetching a first container image in a first virtual machine includes creating a first virtual disk in the shared storage device, storing an image of the first container in the first virtual disk, mounting the first virtual disk to the first virtual machine, and updating a metadata cache to associate the image of the first container to the first virtual disk. Fetching a second container image in a second virtual machine includes checking the metadata cache to determine that a portion of the image of the second container is stored in the first virtual disk, creating a second virtual disk in the shared storage device, adding a reference to the first virtual disk in a metadata of the second virtual disk, and mounting the second virtual disk to the second virtual machine.

Abstract: An example method of configuring a cluster network for an application management system having virtual machines (VMs) executing on a virtualization layer in a cluster of hosts connected to a physical network, wherein the application management system is integrated with the virtualization layer, the method including: deploying, by a virtualization management server, a master server of the application management system prior to configuration of a cluster network that connects the VMs, the master server connected to the virtualization management server by a management network isolated from the cluster network; configuring, by the master server in cooperation with a network manager, the cluster network to connect the VMs; and connecting, by the master server in cooperation with the network manager, the cluster network to an edge node configured to support external ingress/egress for the cluster network.

Abstract: A system and method of performing an incremental backup process are disclosed. In certain aspects, the method comprises retrieving a first metadata associated with a previous backup process of a component from a backup location in a storage. The method further comprises passing the first metadata to the component for determining incremental backup data of the component corresponding to a difference between current data of the component and data of the component associated with the previous backup process. The method further comprises receiving information indicative of the incremental backup data from the component. The method further comprises receiving, from the component, a second metadata associated with the incremental backup process. The method also comprises storing the incremental backup data and the second metadata as associated with the incremental backup process.