Abstract: A method includes receiving a selection of a scan protocol for the scan of a subject and obtaining localizer images including an anatomic landmark of interest of the subject acquired with the MRI system. The method includes automatically detecting the anatomic landmark of interest in localizer images and determining a geometry plan of the scan including extents of the anatomic landmark of interest. The method includes automatically determining a coverage of the scan to include the anatomic landmark of interest and to match the extents of the anatomic landmark of interest. The method includes obtaining limits on adjustments scan time and one or more image quality parameters for the scan protocol. The method includes generating an updated scan protocol by automatically adjusting one or more parameters of the scan protocol based on the scan protocol, the limits on adjustments, and the coverage of the scan.

Abstract: A transceiver for sending and receiving data packets on a communication channel. The transceiver receives a first request packet including a plurality of information fields having a first type of operation to be performed on a memory device and a first address. The transceiver stores the first type of operation and the first address in a memory associated with the transceiver, and sends to a target device, the first request packet with the first address. The transceiver then receives a second request packet, including a second address in the memory device, and determines, based on the first type of operation, the first address, and the second address, that the second request packet is part of a sequence of request packets to the target device. The transceiver then eliminates, in a header of the second request packet, a portion of the second address to form a third request packet and sends the third request packet to the target device.

Abstract: A method is provided. The method include obtaining, from a first system, a set of user requirements associated with one or more storage systems. The method also includes obtaining, from a second system, a set of storage system configurations based on the set of user requirements. The method further includes obtaining, from a third system, a set of costs for the set of storage system configurations. The method further includes generating multimedia content based on the set of storage system configurations, the multimedia content providing information about the set of storage system configurations. The method further includes providing the multimedia content to one or more client devices.

Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

Abstract: A system and method are provided for capturing a high resolution, high frame rate video using a Universal Serial Bus (USB) port. Generally, the method involves transmitting a High-Definition Multimedia Interface (HDMI) video including a number of video frames from a HDMI-source. Receiving the HDMI video and buffering and splitting each one of the video frames into a plurality of split video frames. Each of the split video frames is converted into a number of USB data packets. USB data packets from each of the split video frames are then interleaved to form a stream of USB data packets. The stream of USB data packets is coupled to a host system, which executes a program to stitch the USB data packets back together to reassemble each of the video frames, and order the video frames to restore or recreate the HDMI video.

Abstract: In various examples, when a bridge of a chip has received an eviction request from a client of the chip, the bridge may transmit a read request that corresponds to the same cache line to another chip without waiting for an inter-chip completion response for the eviction request. When the read request is received, the bridge may determine whether the eviction request has already been sent to the other chip and transmit the read request based at least on the eviction request being sent to the other chip using an ordered communication network to ensure the communications are received and/or processed by the other chip in an order that maintains memory coherency. Additionally, the chips may process read unique requests without using an inter-chip completion acknowledgement and may process copy back requests by transmitting corresponding copy back write data with the copy back requests.

Abstract: A device includes an array powered between virtual supply and reference voltages, with each row having a wordline and each column having a bitline and complementary bitline. The virtual supply voltage circuit includes a first transistor configured to output the virtual supply voltage, and a second transistor configured to turn off to reduce current supplied to the array. A column driver, while the second transistor is off, drives the bitlines and complementary bitlines to opposite logic states in response to an internal clock. A row decoder asserts wordlines in response to the internal clock. Due to the reduced current supplied to the array, the bitlines remain at a logic high state and the complementary bitlines fall to a logic-low state, resetting the memory cells.

Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

Abstract: A method for magnetic resonance imaging (MRI) includes determining a Partial Fourier (PF) factor and an acceleration factor for acquiring k-space data from a subject. The method also includes acquiring a set of k-space data from the subject using the PF factor along with an under-sampling technique, wherein the under-sampling technique is dependent on the acceleration factor. The image of the subject is reconstructed by processing the set of k-space data using a deep learning (DL) network.

Abstract: A method includes obtaining k-space data acquired by an MRI scanner from a single channel body coil utilizing a multi-shot EP-DWI pulse sequence and sampling the k-space data for a plurality of shots so that for each shot both a central k-space is fully sampled to form a central calibration region and an outer k-space is partially sampled by a factor equal to a number of shots. The method includes reconstructing an initial fully sampled k-space estimate for each shot utilizing both partial Fourier constant sampling and projection on convex sets reconstruction, wherein the plurality of shots is treated as a plurality of channels for filling in missing k-space for a respective shot. The method includes utilizing a low-rank regularization algorithm in an iterative manner to generate a reconstructed image for each shot, wherein the initial fully sampled k-space estimate for each shot is utilized as an initial guess.

Abstract: A method includes acquiring an MRI complex signal having a plurality of complex echoes during an SWI sequence. The method includes phase filtering each complex echo of the plurality of complex echoes. The method also includes generating a respective phase image and a respective magnitude image from each phase filtered complex echo. The method further includes combining separately the respective magnitude images of the plurality of complex echoes with each other to generate a combined magnitude image and the respective phase images of the plurality of complex echoes with each other to generate a combined phase image. The method includes generating a complex image from both the combined magnitude image and the combined phase image. The method includes utilizing a deep learning-based denoising network to denoise the complex image to generate a denoised complex image.

Abstract: A method for performing a scan of a subject utilizing a magnetic resonance imaging (MRI) system includes triggering a prescan by an MRI scanner of the MRI system upon the subject being setup on a table of the MRI scanner and the table reaching an iso-center of the MRI scanner. The method includes subsequent to the prescan, triggering a calibration scan of the subject with the MRI scanner, wherein the calibration scan is an acoustic noise suppressed MRI scan. The method includes obtaining calibration data from the calibration scan. The method includes obtaining prescription parameters for subsequent scans of the subject with the MRI scanner from the calibration data. The method includes triggering at least one scan of the subject with the MRI scanner based on the prescription parameters.

Abstract: A computer-implemented method, computer-readable medium and computer system to execute containerized applications includes initiating a Supervisor Cluster on top of a SDDC to support execution of containerized applications. A supervisor cluster namespace is created on the Supervisor Cluster. A storage policy is attached to the supervisor cluster namespace. Then, a control plane is bootstrapped, and containerized applications are executed in a virtual machine cluster using vSphere pods as the worker nodes in the virtual machine cluster.

Abstract: An example method of configuring a cluster network for an application management system having virtual machines (VMs) executing on a virtualization layer in a cluster of hosts connected to a physical network, wherein the application management system is integrated with the virtualization layer, the method including: deploying, by a virtualization management server, a master server of the application management system prior to configuration of a cluster network that connects the VMs, the master server connected to the virtualization management server by a management network isolated from the cluster network; configuring, by the master server in cooperation with a network manager, the cluster network to connect the VMs; and connecting, by the master server in cooperation with the network manager, the cluster network to an edge node configured to support external ingress/egress for the cluster network.

Abstract: An electrical apparatus includes: a first electrically conductive contact; and a switch. The switch includes: an electrically conductive moveable contact; a cam; an actuator connected to the electrically conductive moveable contact, the actuator including a cam region configured to interact with the cam. Rotation of the cam moves the actuator between one of two stable positions, the two stable positions including a first position and a second position. The switch also includes an elastic assembly coupled to the actuator, the elastic assembly configured to hold the actuator in either of the two stable positions. When the actuator is in the first position, the switch is closed and the electrically conductive moveable contact is connected to the first electrically conductive contact; and, when the actuator is in the second position, the switch is open and the electrically conductive moveable contact is separated from the first electrically conductive contact.

Abstract: A method comprises creating an electronic module design having a plurality of electronic components comprising a plurality of low power enabled components and defining a model of functional behavior and of power behavior. The method also comprises identifying sequential element information correlated with an electronic component based on the models of functional and power behavior. the sequential element information comprising a first control signal and a second control signal. A coverage test is generated based on the sequential element information and is configured to quantify behavior of the electronic component based on a relationship of a plurality of activation states of a first control signal to a plurality of activation states of a second control signal. A simulation file is run to simulate operation of the electronic module design, and a performance status of the electronic module design is determined in response to running the simulation file.

Abstract: Container images are fetched in a clustered container host system with a shared storage device. Fetching a first container image in a first virtual machine includes creating a first virtual disk in the shared storage device, storing an image of the first container in the first virtual disk, mounting the first virtual disk to the first virtual machine, and updating a metadata cache to associate the image of the first container to the first virtual disk. Fetching a second container image in a second virtual machine includes checking the metadata cache to determine that a portion of the image of the second container is stored in the first virtual disk, creating a second virtual disk in the shared storage device, adding a reference to the first virtual disk in a metadata of the second virtual disk, and mounting the second virtual disk to the second virtual machine.

Abstract: A device may process data associated with a first entity and a second entity, using one or more machine learning techniques, to identify a set of trends associated with a set of documents. The device may receive new documents associated with the first entity and the second entity. The device may generate, based on the set of trends, a first set of exceptions indicating that a new document is associated with a first type of error. The device may generate, using a similarity analysis technique, a second set of exceptions indicating that a new document is associated with a second type of error. The device may communicate with one or more systems to perform one or more actions associated with correction or prevention of processing errors relating to the new document based a claim relating to the first set of exceptions or the second set of exceptions.