Abstract: A system and method of performing an incremental backup process are disclosed. In certain aspects, the method comprises retrieving a first metadata associated with a previous backup process of a component from a backup location in a storage. The method further comprises passing the first metadata to the component for determining incremental backup data of the component corresponding to a difference between current data of the component and data of the component associated with the previous backup process. The method further comprises receiving information indicative of the incremental backup data from the component. The method further comprises receiving, from the component, a second metadata associated with the incremental backup process. The method also comprises storing the incremental backup data and the second metadata as associated with the incremental backup process.

Abstract: A mobile phone case adapted to accommodate a mobile phone device having a mirrored surface attached is disclosed. The mirrored surface is preferably attached to the back side of the phone case. Alternatively, the case may be a folding type case having the phone on one side and the mirrored surface on the other. The phone case attaches substantially to the rear of the mobile phone, and preferably includes openings which align with phone components. A plurality of LEDs are disposed about the perimeter of the mirrored surface, allowing the object of the reflection to be illuminated. The LEDs may derive power from the phone power source or from a separate power source such as one or more button cell or rechargeable batteries. Optionally, the LEDs are dimmable via a control.

Abstract: A device may determine one or more trends by using one or more machine learning techniques to process historical transactional information included in a set of historical transactional documents. The device may receive a set of transactional documents associated with transactions between a client organization and a vendor organization. The device may generate, based on the one or more trends, a first set of exceptions indicating that one or more transactional documents are problematic transactional documents. The device may generate, using a similarity analysis technique, a second set of exceptions indicating that one or more additional transactional documents are duplicate transactional documents. The device may generate a set of claims based on one or more exceptions. The device may perform, based on the set of claims, one or more actions associated with correction or prevention of transaction processing errors relating to the set of transactional documents.

Abstract: A method may include receiving, from multiple, different sources, documents. The documents may be received in multiple, different file formats. The method may include performing operations on the documents to prepare the documents for processing, to obtain data included in the documents, or to determine information describing the documents. The method may include storing or providing, for storage, status information corresponding to the documents. The status information for a document may identify results of performing the operations with regard to the document. The method may include receiving an instruction that identifies an action to perform with regard to the document. The method may include performing the action. The method may include updating the status information to generate updated status information based on a result of performing the action. The method may include providing the updated status information.

Abstract: A method in a network controller and an apparatus for visual logging is described. The method includes receiving one or more log entries from one of a plurality of network elements in a network, wherein the one or more log entries indicate the occurrence of one or more events on the network; converting the one or more log entries into one or more graph log entries using a set of one or more graph log commands, wherein log entries of a certain type are associated with a corresponding graph identifier; and storing the one or more graph log entries in a graph log file of the corresponding graph identifier.

Abstract: An apparatus and method for branch prediction are disclosed. The branch predictor has four portions. The first includes a bimodal branch predictor in series with a local branch predictor; the second includes a global branch predictor. The first and second portions are in parallel and operate concurrently, and each provide an output received by the fourth portion. The third portion receives address data and selection data, and also provides output to the fourth portion. The fourth portion receives these outputs, and provides a branch prediction. The branch prediction is a selection of either the output from the first portion or the output from the second portion, based upon selection criteria received from the third portion.

Abstract: An error correction code apparatus has a processor located (on-chip) L2 tag and error correction and detection, and an off-chip L2 data array and second error correction and detection, the chips connected by a data bus. For a write operation, ECC bits are generated and transmitted with data to the off-chip array. New ECC bits are generated and compared to the original ECC bits. Correction is accomplished if needed. For a read operation, stored ECC bits and data are retrieved from the off-chip data array and transmitted to the core processor. New ECC bits are generated and compared to the original ECC bits. Correction is accomplished if needed.

Abstract: A branch prediction architecture is disclosed, having a branch predictor, a target address register, first and second multiplexors, a cache memory, and a trace cache. The branch predictor may advantageously be a series-parallel branch predictor, and alternatively may be a serial-BLG branch predictor or a choosing branch predictor. The first multiplexor receives an input from the target address register, and provides an output to the cache memory. The cache memory receives output from both the branch predictor and the first multiplexor, and provides an output to the second multiplexor. The trace cache receives the output from the branch predictor, and provides an output received by the second multiplexor. The second multiplexor, receiving input from both the trace cache and the cache memory, outputs branch predictions and instruction bundles.

Abstract: The present invention provides an improved cache memory architecture with way prediction. The improved architecture entails placing the address tag array of a cache memory on the central processing unit core (i.e. the microprocessor chip), while the cache data array remains off the microprocessor chip. In addition, a way predictor is provided in conjunction with the improved memory cache architecture to increase the overall performance of the cache memory system.

Abstract: The present invention provides a method and a data processing system for accessing a memory of a data processing system, the data processing system including a first and at least a second level memory for storing information. The method includes issuing a memory request to the first level memory, and issuing the memory request to the second level memory at substantially the same time the memory request is issued to the first level memory.

Abstract: An apparatus and method for managing a memory is disclosed. A discharging unit discharges overcharged bit lines in memory. The discharging unit discharges the bit lines after a predetermined time after the last memory access. The discharging unit also discharges the bit lines after a microprocessor comes out of a low power mode.