Patents by Inventor Harsh Naik

Harsh Naik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10868173
    Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Cedric Ouvrard, Adam Amali, Oliver Blank, Michael Hutzler, David Laforet, Harsh Naik, Ralf Siemieniec, Li Juin Yip
  • Publication number: 20200328303
    Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Inventors: Cedric Ouvrard, Adam Amali, Oliver Blank, Michael Hutzler, David Laforet, Harsh Naik, Ralf Siemieniec, Li Juin Yip
  • Patent number: 10727331
    Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Cedric Ouvrard, Adam Amali, Oliver Blank, Michael Hutzler, David Laforet, Harsh Naik, Ralf Siemieniec, Li Juin Yip
  • Publication number: 20200203525
    Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 25, 2020
    Inventors: Robert Paul Haase, Jyotshna Bhandari, Heimo Hofer, Ling Ma, Ashita Mirchandani, Harsh Naik, Martin Poelzl, Martin Henning Vielemeyer, Britta Wutte
  • Publication number: 20190006513
    Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 3, 2019
    Inventors: Cedric Ouvrard, Adam Amali, Oliver Blank, Michael Hutzler, David Laforet, Harsh Naik, Ralf Siemieniec, Li Juin Yip
  • Publication number: 20170288066
    Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.
    Type: Application
    Filed: June 20, 2017
    Publication date: October 5, 2017
    Inventors: Madhur Bobde, Harsh Naik, Lingping Guan, Anup Bhalla, Sik Lui
  • Patent number: 9685523
    Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: June 20, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Harsh Naik, Lingpeng Guan, Anup Bhalla, Sik Lui
  • Patent number: 9590096
    Abstract: In one implementation, a vertical field-effect transistor (FET) includes a substrate having a drift region situated over a drain, a body region situated over the drift region and having source diffusions formed therein, a gate trench extending through the body region, and channel regions adjacent the gate trench. The channel regions are spaced apart along the gate trench by respective deep body implants. Each of the deep body implants is situated approximately under at least one of the source diffusions, and has a depth greater than a depth of the gate trench.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: March 7, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Harsh Naik, Timothy D. Henson, Niraj Ranjan
  • Publication number: 20160181391
    Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Inventors: Madhur Bobde, Harsh Naik, Lingpeng Guan, Anup Bhalla, Sik Lui
  • Publication number: 20160172484
    Abstract: In one implementation, a vertical field-effect transistor (FET) includes a substrate having a drift region situated over a drain, a body region situated over the drift region and having source diffusions formed therein, a gate trench extending through the body region, and channel regions adjacent the gate trench. The channel regions are spaced apart along the gate trench by respective deep body implants. Each of the deep body implants is situated approximately under at least one of the source diffusions, and has a depth greater than a depth of the gate trench.
    Type: Application
    Filed: November 16, 2015
    Publication date: June 16, 2016
    Inventors: Harsh Naik, Timothy D. Henson, Niraj Ranjan
  • Publication number: 20160172295
    Abstract: In one implementation, a power field-effect transistor (FET) having a reduced gate resistance includes a drain, a source, a gate, and a gate contact including a gate pad, a gate highway, and multiple gate buses. The gate buses are formed from a first metal layer having a first thickness, while the gate pad and the gate highway each include a metal stack including the first metal layer and a second metal layer. The second metal layer has a second thickness substantially greater than the first thickness, thereby reducing the gate resistance of the power FET.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 16, 2016
    Inventors: Alex Lollio, Timothy D. Henson, Ling Ma, Harsh Naik, Niraj Ranjan
  • Patent number: 8933506
    Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: January 13, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Harsh Naik, Lingpeng Guan, Anup Bhalla, Sik Lui
  • Publication number: 20120193676
    Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 2, 2012
    Inventors: Madhur Bobde, Harsh Naik, Lingpeng Guan, Anup Bhalla, Sik Lui