Abstract: A semiconductor device includes: a semiconductor substrate; a drift zone of a first conductivity type in the semiconductor substrate; an array of interconnected gate trenches extending from a first surface of the semiconductor substrate into the drift zone; a plurality of semiconductor mesas delimited by the array of interconnected gate trenches; a plurality of needle-shaped field plate trenches extending from the first surface into the plurality of semiconductor mesas; in the plurality of semiconductor mesas, a source region of the first conductivity type and a body region of a second conductivity type separating the source region from the drift zone; and a current spreading region of the first conductivity type at the bottom of the gate trenches and having a higher average doping concentration than the drift zone. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device includes: a plurality of transistor cells formed in a semiconductor body. The plurality of transistor cells includes: a plurality of stripe-shape gate trenches formed in a first main surface of the semiconductor body; and a plurality of field plate trenches separate from the stripe-shape gate trenches. At least one field plate trench is laterally interposed between each pair of neighboring stripe-shape gate trenches. Each stripe-shape gate trench includes a gate electrode, a gate dielectric between the gate electrode and a sidewall of the stripe-shape gate trench, and an oxide between the gate electrode and a bottom of the stripe-shape gate trench, the oxide having a vertical thickness that is greater than eight times a lateral thickness of the gate dielectric and/or greater than a vertical thickness of the gate electrode. A method of producing the semiconductor device is also described.

Abstract: A semiconductor device is described. The semiconductor device includes: a semiconductor substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the semiconductor substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

Abstract: A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.

Abstract: A semiconductor die includes: a silicon substrate; a trench gate NMOS transistor formed in a first device region of the silicon substrate; a trench gate PMOS transistor formed in a second device region of the silicon substrate and electrically connected to the trench gate NMOS transistor; and an isolation structure interposed between the first device region and the second device region. Methods of monolithically integrating the trench gate NMOS transistor and the trench gate PMOS transistor in the same semiconductor die are also described.

Abstract: A semiconductor device is described. The semiconductor device includes: a semiconductor substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the semiconductor substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device is described. The semiconductor device includes: a Si substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the Si substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

Abstract: In an embodiment, a semiconductor device is provided that includes: a vertical power FET configured to switch a load current and provide a channel of a first conductivity type; and a lateral FET configured to drive the vertical power FET and provide a channel of a second conductivity type opposing the first conductivity type. The vertical power FET and the lateral FET are monolithically integrated into a semiconductor substrate of the first conductivity type and a drain of the lateral FET is electrically coupled to a gate of the vertical power FET.

Abstract: In an embodiment, a semiconductor device includes a vertical power FET for switching a load current, the power FET including a channel region of a first conductivity type and a first lateral FET and a second lateral FET providing an output stage of gate driver circuitry for driving the power FET. The first lateral FET includes a channel region of the first conductivity type and the second lateral FET includes a channel region of a second conductivity type opposing the first conductivity type. The power FET and the first and second lateral FETs are monolithically integrated into a semiconductor substrate of the first conductivity type and that has a first surface. A drain of the first lateral FET and a source of the second lateral FET are electrically coupled to a gate of the power FET.

Abstract: A semiconductor device includes: a semiconductor substrate; a drift zone of a first conductivity type in the semiconductor substrate; an array of interconnected gate trenches extending from a first surface of the semiconductor substrate into the drift zone; a plurality of semiconductor mesas delimited by the array of interconnected gate trenches; a plurality of needle-shaped field plate trenches extending from the first surface into the plurality of semiconductor mesas; in the plurality of semiconductor mesas, a source region of the first conductivity type and a body region of a second conductivity type separating the source region from the drift zone; and a current spreading region of the first conductivity type at the bottom of the gate trenches and having a higher average doping concentration than the drift zone. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device is described. The semiconductor device includes: a Si substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the Si substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

Abstract: A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.

Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.

Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.

Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.

Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate having drift and body regions. The drift region includes upper and lower drift regions. An active area includes a plurality of spicular trenches extending through the body region and into the drift region. Each spicular trench in the active area has a lower end which together define a lower end of the upper drift region extending towards a first side and a lower drift region extending from the lower end of the upper drift region towards a second side. The edge termination area includes spicular termination trenches extending at least into the upper drift region. A surface doping region arranged in the upper drift region in the edge termination area extends to the first side, is spaced apart from the lower end of the upper drift region, and has a net doping concentration lower than that of the upper drift region.

Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.