Abstract: An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.

Abstract: An electronic device comprising multilevel bitlines, pillar contacts, level 1 contacts, and level 2 contacts. The multilevel bitlines comprise first bitlines and second bitlines, with the first bitlines and second bitlines positioned at different levels. The pillar contacts are electrically connected to the first bitlines and to the second bitlines, the level 1 contacts are electrically connected to the first bitlines, and the level 2 contacts are electrically connected to the second bitlines. Each bitline of the first bitlines is electrically connected to a single pillar contact adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

Abstract: Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.

Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure having an alternating sequence of conductive structures and insulative structures, an upper stadium structure, a lower stadium structure, and a crest region defined between a first stair step structure of the upper stadium structure and a second stair step structure of the lower stadium structure. The stack structure further includes pillar structures extending through the stack structure and dielectric structures interposed between neighboring pillar structures within the upper stadium structure. The method further includes forming a trench in the crest region of the stack structure between two dielectric structures of the dielectric structures on opposing sides of another dielectric structure and filling the trench with a dielectric material. The trench partially overlaps with the dielectric structures.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses.

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The stack structure comprises a first block structure comprising stair step structures spaced from each other by crest regions, the stair step structures each comprising steps defined at horizontal edges of the tiers of the conductive structures and the insulative structures, and a second block structure horizontally neighboring the first block structure and comprising additional stair step structures spaced from one another by additional crest regions, the additional stair step structures horizontally offset from the stair step structures of the first block structure, and a slot structure extending though the stack structure and interposed between the first block structure and the second block structure. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, a first insulative material vertically overlying the staircase structure, conductive contact structures comprising a conductive material extending through the first insulative material and in contact with the steps of the staircase structure, and a second insulative material extending in a first horizontal direction between horizontally neighboring conductive contact structures and exhibiting one or more different properties than the first insulative material. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of slit structures extends through the stack structure and devices the stack structure into a series of blocks. In a progressed portion of the series of blocks, each block comprises an array of pillars extending the through the stack structure of the block. Also, each block—in the progressed portion—has a different block width than a block width of a neighboring block of the progressed portion of the series of blocks. At least one pillar, of the pillars of the array of pillars in the progressed portion, exhibits bending. Related methods and electronic systems are also disclosed.

Abstract: A microelectronic device comprises a first deck structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, a second deck structure vertically overlying the first deck structure and comprising additional tiers of the conductive structures and insulative structures, a staircase structure within the first deck structure and having steps comprising edges of the tiers, a dielectric material covering the steps of the staircase structure and extending through the first deck structure, and a liner material interposed between the steps of the staircase structure and terminating at an interdeck region between the first deck structure and the second deck structure. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers having channel-material strings therein. Conductive vias are formed through insulating material that is directly above the channel-material strings. Individual of the conductive vias are directly electrically coupled to individual of the channel-material strings. After forming the conductive vias, horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Intervening material is formed in the trenches laterally-between and longitudinally-along the immediately-laterally-adjacent memory-block regions. Additional methods and structures independent of method are disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers having channel-material strings therein. Conductive vias are formed through insulating material that is directly above the channel-material strings. Individual of the conductive vias are directly electrically coupled to individual of the channel-material strings. After forming the conductive vias, horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Intervening material is formed in the trenches laterally-between and longitudinally-along the immediately-laterally-adjacent memory-block regions. Additional methods and structures independent of method are disclosed.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers having channel-material strings therein. Conductive vias are formed through insulating material that is directly above the channel-material strings. Individual of the conductive vias are directly electrically coupled to individual of the channel-material strings. After forming the conductive vias, horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Intervening material is formed in the trenches laterally-between and longitudinally-along the immediately-laterally-adjacent memory-block regions. Additional methods and structures independent of method are disclosed.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

Abstract: An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.