Patents by Inventor HARSH

HARSH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12176866
    Abstract: Described are circuits and techniques to increase the efficiency of radio-frequency (rf) amplifiers including rf power amplifiers (PAs) through “supply modulation” (also referred to as “drain modulation” or “collector modulation”), in which supply voltages provided to rf amplifiers is adjusted dynamically (“modulated”) over time depending upon the rf signal being synthesized. For the largest efficiency improvements, a supply voltage can be adjusted among discrete voltage levels or continuously on a short time scale. The supply voltages (or voltage levels) provided to an rf amplifier may also be adapted to accommodate longer-term changes in desired rf envelope such as associated with adapting transmitter output strength to minimize errors in data transfer, for rf “traffic” variations.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: December 24, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: James Garrett, Sri Harsh Pakala, Brendan Metzner, Ivan Duzevik, David J. Perreault, John R. Hoversten, Yevgeniy A. Tkachenko
  • Patent number: 12176025
    Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: December 24, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Nitin Chawla, Manuj Ayodhyawasi
  • Patent number: 12176867
    Abstract: Described are circuits and techniques to increase the efficiency of radio-frequency (rf) amplifiers including rf power amplifiers (PAs) through “supply modulation” (also referred to as “drain modulation” or “collector modulation”), in which supply voltages provided to rf amplifiers is adjusted dynamically (“modulated”) over time depending upon the rf signal being synthesized. For the largest efficiency improvements, a supply voltage can be adjusted among discrete voltage levels or continuously on a short time scale. The supply voltages (or voltage levels) provided to an rf amplifier may also be adapted to accommodate longer-term changes in desired rf envelope such as associated with adapting transmitter output strength to minimize errors in data transfer, for rf “traffic” variations.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: December 24, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: James Garrett, Sri Harsh Pakala, Brendan Metzner, Ivan Duzevik, David J. Perreault, John R. Hoversten, Yevgeniy A. Tkachenko
  • Publication number: 20240419995
    Abstract: The present disclosure relates to a dataset exploration system based on input data having a plurality of data samples having a plurality of features. In particular, the systems described herein generate preprocessed input data including one or more of performing data normalization, calculating covariance matrix, and assessing data quality of the preprocessed input data. The system further generates a domain structure from the preprocessed input data. The system further includes recovering a probabilistic graphical model (PGM) trained to discover the underlying joint distribution over the plurality of features based on the preprocessed input data and the domain structure. The learned PGM may be utilized to answer user queries by leveraging its probabilistic inference capabilities on the data and various different visual outputs may be presented via a display device.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 19, 2024
    Inventors: Urszula Stefania CHAJEWSKA, Harsh SHRIVASTAVA
  • Publication number: 20240419540
    Abstract: Aspects of the embodiments disclosed herein include employing data stored on a first memory cell to recover lost data that cannot be retrieved from a second memory cell, for example, due to data loss or damage to the second memory cell. In one embodiment, the first memory cell and the second memory cell are part of the same computer memory assembly, such as the same SSD, and are directly linked to each other. In one embodiment, the first memory cell stores, among other things, a first special address location that references a location of the second memory cell and metadata of the second memory cell. In one embodiment, the first special address location is used to retrieve lost data from the second memory cell, thereby providing a computationally inexpensive technique for recovering lost data without the need for performing traditional computationally expensive backup operations across datacenters.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 19, 2024
    Inventor: Harsh P BAJAJ
  • Publication number: 20240419499
    Abstract: A method for dynamic estimation of time-to-completion may include: receiving historical ticket data for historical tickets, the historical ticket data comprising historical tasks for each historical ticket; assigning each of the historical tasks into one of a plurality of buckets based on a common feature; training, for each bucket, a trained machine learning engine to predict a time-to-completion for the tasks in the bucket; receiving a current ticket; determining a plurality of tasks and an order of executing the tasks for the current ticket; identifying one of the buckets for each of the tasks in the current ticket; predicting, for each task in the current ticket, the time-to-completion for the current using the trained machine learning engine for the bucket for the task; combining the time-to-completion for the tasks for the current ticket into a current ticket time-to-completion; and returning the current ticket time-to-completion for the current ticket.
    Type: Application
    Filed: June 14, 2023
    Publication date: December 19, 2024
    Inventors: Vahid GOLKHOU, Loryfel NUNEZ, Samantha ZUCKER, Anirban ROY, Rebecca E. LAVAULT, Harsh PATEL
  • Publication number: 20240420165
    Abstract: Apparatuses, methods, and systems for detecting changes in customer behavior are disclosed. One method includes detecting customer action data, receiving, by a marketing platform server, the customer action data over a period of time, determining, customer parameters including a mean, and a standard deviation of the customer action data, generating a normalization value when the standard deviation is detected to be less than a deviation threshold, calculating, by the marketing platform server, a value of deviation from expectation based at least on the mean, the normalization value, and a noise factor, calculating a current cumulative sum value of the customer action data based on a prior cumulative sum value and the value of the deviation from expectation, comparing the current cumulative sum value with a threshold, and generating an electronic communication for the merchant server when the current cumulative sum value satisfies a compared condition with the preselected threshold.
    Type: Application
    Filed: August 30, 2024
    Publication date: December 19, 2024
    Applicant: Klaviyo, Inc
    Inventors: Olof Jacobson, Harsh Mehta
  • Patent number: 12169524
    Abstract: The present disclosure relates to methods and systems for querying data in a data repository. According to a first aspect, this disclosure describes a method of querying a database, comprising: receiving, at a computing device, a plurality of keywords; determining, by the computer device, a plurality of datasets relating to the keywords; identifying, by the computer device, metadata for the plurality of datasets indicating a relationship between the datasets by examining an ontology associated with the datasets; providing, by the computer device, one or more suggested database queries in natural language form, the one or more suggested database queries constructed based on the plurality of keywords and the metadata; receiving, by the computing device, a selection of the one or more suggested database queries; and constructing, by the computer device, an object view for the plurality of datasets based on the selected query and the metadata.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: December 17, 2024
    Assignee: Palantir Technologies Inc.
    Inventors: Cenk Sezgin, Advaya Krishna, Adhish Ramkumar, Arthur Wu, Adam Wiles, Gregory Slonim, Harsh Pandey, Kushal Nigam, Michal Adamczyk
  • Patent number: 12169680
    Abstract: The present disclosure relates to methods and systems for converting Portable Document Format (PDF) documents to LaTeX files. The methods and systems use machine learning models to identify and extract PDF portions of a PDF document. The methods and systems create a LaTeX file for the PDF document using the PDF portions extracted by the machine learning models. The methods and systems provide an output with the LaTeX file for the PDF document. The LaTeX file is used to perform different actions on the PDF document.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: December 17, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Harsh Shrivastava, Sarah Panda, Liang Du, Robin Abraham
  • Patent number: 12170120
    Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: December 17, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Hitesh Chawla, Tanuj Kumar, Bhupender Singh, Harsh Rawat, Kedar Janardan Dhori, Manuj Ayodhyawasi, Nitin Chawla, Promod Kumar
  • Publication number: 20240411779
    Abstract: This disclosure relates to a time series segmentation system that efficiently and accurately segments univariate time series data. For example, the time series segmentation system utilizes proxy variable time series to identify distinct segments in a univariate time series. To illustrate, the time series segmentation system generates proxy variables that approximate a univariate time series and combine with the time series to generate a supplemented multivariate time series. The time series segmentation system then divides the supplemented multivariate time series into portions using time-based windows, converts the windowed subsequences into graph objects using a sparse graph recovery model, utilizes a conditional similarity model to determine segmentation timestamps from the graph objects, and generates a segmented univariate time series from the segmentation timestamps.
    Type: Application
    Filed: March 24, 2023
    Publication date: December 12, 2024
    Inventors: Harsh SHRIVASTAVA, Shima IMANI
  • Patent number: 12164936
    Abstract: The method includes receiving a process dataset. The process dataset includes data related to a user-executed process. The method also includes automatically mapping the process dataset to multisource system data deemed relevant to automation of the user-executed process. The method also includes detecting a plurality of scenarios in the user-executed process via the automatically mapped process dataset. The method also includes performing scenario-based filtering of the plurality of scenarios. The method also includes automatically generating an automation recommendation for the user-executed process.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: December 10, 2024
    Assignee: NTT DATA Services, LLC
    Inventors: Sankar Chandrasekaran, Krishnavelu Puliyuran, Jeyarani Rajadurai, Tanvir Khan, Harsh Vinayak, Dhurai Ganesan
  • Publication number: 20240406231
    Abstract: A data processing system implements a hybrid environment for interactions between remote and in-person users. The data processing techniques provide tools for facilitating mingling of remote and in-person users in semi-structured interaction, such as but not limited to tradeshows or conferences, and unstructured interactions, such as but not limited to social gatherings that solve the technical problems associated with enabling such systems. The data processing system implements audio porosity and map-based navigation to facilitate improved spatial awareness and awareness of the presence of other remote or in-person users nearby with whom the user can interact.
    Type: Application
    Filed: July 25, 2023
    Publication date: December 5, 2024
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Venkata N. PADMANABHAN, Ajay MANCHEPALLI, Harsh VIJAY, Sirish GAMBHIRA, Amish MITTAL, Saumay PUSHP, Praveen GUPTA, Mayank BARANWAL, Shivang CHOPRA, Meghna GUPTA, Arshia ARYA
  • Publication number: 20240403200
    Abstract: This disclosure describes techniques that include validation or other assessments of digital systems, such as machine learning models and other statistical models. In one example, this disclosure describes a method that includes receiving, by a validation computing system and from a development system, a request to perform a test on a model configured to execute on the development system; outputting, by the validation computing system to the development system and in response to the request, an instruction; enabling the development system to process the instruction; receiving, by the validation computing system, test response data; evaluating, by the validation system, the test response data.
    Type: Application
    Filed: August 15, 2024
    Publication date: December 5, 2024
    Inventors: Fernando Cela Diaz, Agus Sudjianto, Harsh Singhal, Ningzhou Zeng, Kai Arne Krueger, Harsh Vardhan Tiwari, Ridhi Puppala, Karan H. Jeswani
  • Publication number: 20240405120
    Abstract: A semiconductor device includes: a plurality of transistor cells formed in a semiconductor body. The plurality of transistor cells includes: a plurality of stripe-shape gate trenches formed in a first main surface of the semiconductor body; and a plurality of field plate trenches separate from the stripe-shape gate trenches. At least one field plate trench is laterally interposed between each pair of neighboring stripe-shape gate trenches. Each stripe-shape gate trench includes a gate electrode, a gate dielectric between the gate electrode and a sidewall of the stripe-shape gate trench, and an oxide between the gate electrode and a bottom of the stripe-shape gate trench, the oxide having a vertical thickness that is greater than eight times a lateral thickness of the gate dielectric and/or greater than a vertical thickness of the gate electrode. A method of producing the semiconductor device is also described.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 5, 2024
    Inventors: Timothy Henson, Harsh Naik, Oliver Blank, Gerhard Thomas Nöbauer
  • Patent number: 12159689
    Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: December 3, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Praveen Kumar Verma, Promod Kumar, Harsh Rawat
  • Patent number: 12158920
    Abstract: A method converts a request received from a client application to a query by a serverless function operating on a virtual machine instance provisioned responsive to the request. The query is transmitted to an application database corresponding to the client application. A result is received from the application database. The result is converted into a response and the response is transmitted to the client application in response to the request. Display of the client application is updated based on response with the result.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: December 3, 2024
    Assignee: Intuit Inc.
    Inventors: Ashwith Atluri, Havyas H K, Harsh Mohan Modawel
  • Patent number: 12158876
    Abstract: Systems and methods are provided for implementing automated user interface testing with integrated machine learning models. Systems and methods for detecting and preemptively correcting flow path errors are disclosed. Systems and methods for minimizing user input and optimizing testing efficiency are disclosed. A result dashboard is disclosed in which testing results and errors are displayed and a user may interact with interactive testing reports.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: December 3, 2024
    Assignee: FIDELITY INFORMATION SERVICES, LLC
    Inventors: Harsh Sharma, Yogendra Singh Katheria, Seerajudeen Sheik Ahamed, Rajiv Ramanjani, Shefali Garg
  • Patent number: 12159110
    Abstract: The present disclosure relates to systems, methods, and computer-readable media for utilizing a concept graphing system to determine and provide relationships between concepts within document collections or corpora. For example, the concept graphing system can generate and utilize machine-learning models, such as a sparse graph recovery machine-learning model, to identify less-obvious correlations between concepts, including positive and negative concept connections, as well as provide these connections within a visual concept graph. Additionally, the concept graphing system can provide a visual concept graph that determines and displays concept correlations based on the input of a single concept, multiple concepts, or no concepts.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: December 3, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Harsh Shrivastava, Maurice Diesendruck, Robin Abraham
  • Patent number: 12160208
    Abstract: Described are circuits and techniques to increase the efficiency of radio-frequency (rf) amplifiers including rf power amplifiers (PAs) through “supply modulation” (also referred to as “drain modulation” or “collector modulation”), in which supply voltages provided to rf amplifiers is adjusted dynamically (“modulated”) over time depending upon the rf signal being synthesized. For the largest efficiency improvements, a supply voltage can be adjusted among discrete voltage levels or continuously on a short time scale. The supply voltages (or voltage levels) provided to an rf amplifier may also be adapted to accommodate longer-term changes in desired rf envelope such as associated with adapting transmitter output strength to minimize errors in data transfer, for rf “traffic” variations.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: December 3, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: James Garrett, Sri Harsh Pakala, Brendan Metzner, Ivan Duzevik, David J. Perreault, John R. Hoversten, Yevgeniy A. Tkachenko