Abstract: A forksheet FET device and processes for fabricating the same are provided. A semiconductor device includes a dielectric wall; a first semiconductor layer extending in a first direction perpendicular from a first side of the dielectric wall, the first semiconductor layer having a first end that is nearest to the dielectric wall; and a first gate electrode layer including a first gate extension that extends beyond the first end of the first semiconductor layer nearer to the first side of the dielectric wall.

Abstract: A device includes a two transistor zero capacitor gain cell that is back end of line compatible and includes a write transistor and a read transistor that is electrically connected to the write transistor. The write transistor includes an oxide semiconductor channel and the read transistor includes a polysilicon channel.

Abstract: Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

Abstract: A method for depositing a film includes conducting electron-enhanced chemical vapor deposition with at least one hydride precursor, at least one reactive background gas, and electrons to deposit a film on a substrate with a positive substrate voltage. In an embodiment, the method is a method for depositing a silicon film, including conducting electron-enhanced chemical vapor deposition with at least one Si precursor, at least one reactive background gas, and electrons to deposit a silicon film on a substrate with a positive substrate voltage. In the embodiment, the at least one Si precursor can include Si2H6 and the at least one reactive background gas can include H2.

Abstract: A method for etching a thin film includes conducting electron-enhanced chemical vapor etching with at least one reactive background gas and electrons to etch a thin film on a substrate with a positive substrate voltage. In an embodiment, the method is a method for etching a silicon thin film, including conducting electron-enhanced chemical vapor etching with at least one reactive background gas and electrons to etch a silicon thin film on a substrate with a positive substrate voltage.

Abstract: Described are low resistivity metal layers/films, such as low resistivity ruthenium (Ru) layers/films, and methods of forming low resistivity metal films. Ru layers/films with close-to-bulk resistivity can be prepared on substrates using Ru(CpEt)2+O2 ALD, as well as a two-step ALD process using Ru(DMBD)(CO)3+TBA (tertiary butyl amine) to nucleate the substrate and Ru(EtCp)2+O2 to increase layer/film thickness. The Ru layer/films and methods of preparing Ru layers/films described herein may be suitable for use in barrierless via-fills, as well as at M0/M1 interconnect layers.

Abstract: Disclosed herein are methods, devices and systems including a substrate, a transistor channel on the substrate and extending in direction parallel to the substrate, a first electrode extending in a direction orthogonal to the substrate and coupled to the transistor channel, a second electrode coupled to the transistor channel and extending in a direction orthogonal to the substrate and parallel to the first electrode, and a first epitaxial structure arranged between the transistor channel and the first electrode. The first epitaxial structure may share a common crystalline orientation with the transistor channel, and may separate a surface of the first electrode and a surface of the transistor channel in a direction parallel to the substrate by a distance varying along the length of the first electrode.

Abstract: A method, apparatus, and system are provided. The method includes the steps of depositing a dummy stressor into a source and drain (S/D) region between a first sidewall and a second sidewall of a transistor before an epitaxial (EPI) layer is deposited into the S/D region; removing a polysilicon fin between the second sidewall and a third sidewall of the transistor to expose an initial stack; removing the dummy stressor from the S/D region; and depositing the EPI layer into the S/D region.

Abstract: Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Abstract: A method for forming a metal oxide insulating film includes conducting electron-enhanced atomic layer deposition with at least one metal-containing precursor gas and at least one oxygen-containing precursor gas as reactants to deposit a metal oxide insulating film on a substrate. The metal oxide can be SiO2, TiO2, HfO2, or ZrO2. A particular method for forming a SiO2 film includes conducting electron-enhanced atomic layer deposition with at least one silicon-containing precursor gas and at least one oxygen-containing precursor gas as reactants to deposit a SiO2 film on a substrate, wherein the electron-enhanced atomic layer deposition is conducted at a temperature of less than 300° C. A SiO2 film produced by the method can be a blanket film or a patterned structure.

Abstract: A process for forming a vapor-deposited ZIF-8 metal organic framework includes: conducting a gas surface reaction between an ALD-deposited ZnO and 2-methylimidazole to form a vapor-deposited ZIF-8 metal organic framework, wherein the gas surface reaction is conducted at a temperature greater than 140 C, and wherein the gas surface reaction is conducted at a pressure of less than 1000 mTorr. In a particular embodiment, the gas surface reaction is conducted at a temperature of 160 C. A process for preparing a laminate includes: performing ALD of zinc oxide as a base between 1 nm to 10 nm in thickness, exposing 2-methylimidazole vapor phase linker at chemical vapor deposition at a temperature range of greater than 140 C to less than or equal to 180 C in a vacuum condition, and cycling of the ZnO ALD and 2-methylimidazole exposure to deposit a film or fill a gap.

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Abstract: A method of manufacturing a three-dimensional field-effect transistor including an upper field-effect transistor stacked on a lower field-effect transistor. The method includes epitaxially growing source/drain regions of the lower field-effect effect transistor, growing a sacrificial layer on an upper surface of the source/drain regions, and epitaxially growing source/drain regions of the upper field-effect transistor on the sacrificial layer. The sacrificial layer is a seed layer for the source/drain regions of the upper field-effect transistor. The method also includes selectively etching the sacrificial layer to form a gap between the source/drain regions of the lower field-effect transistor and the source/drain regions of the upper field-effect transistor, and depositing an oxide layer in the gap.

Abstract: An magnetoresistive random access memory (MRAM) device includes a magnetic tunnel junction, and a spin-orbit torque material. Based on a current applied to the spin-orbit torque material, the spin-orbit torque material generates spin polarization along one or multiple axes.

Abstract: Provided are systems, methods, and apparatuses for applying stress in transistors. In one or more examples, the systems, devices, and methods include depositing an epitaxial film on a surface between a first sidewall and a second sidewall of the transistor; depositing a dielectric over the epitaxial film and on the surface between the first sidewall and the second sidewall to increase stress in a silicon channel of the transistor; removing a polysilicon fin between the second sidewall and a third sidewall; and depositing a first metal between the second sidewall and the third sidewall based on removing the polysilicon fin.

Abstract: According to one or more embodiments of the present disclosure, a semiconductor device is described. The semiconductor device may include a substrate, a channel portion on the substrate between a source region and a drain region, and a gate on the channel. The channel portion may include a first portion extending in a first direction and at least one second portion protruding from the first portion in a second direction crossing the first portion.

Abstract: A field-effect transistor includes a substrate, a channel on the substrate including a stem including silicon extending in a vertical direction from the substrate and a number of prongs including silicon extending in a horizontal direction from the stem and spaced apart from each other along the vertical direction, an interfacial layer surrounding the stem and the prongs of the channel, a dielectric layer on the interfacial layer and surrounding the stem and the prongs of the channel, and a metal gate on the dielectric layer and surrounding the stem and the prongs of the channel.

Abstract: A method for manufacturing a semiconductor device according to one or more embodiments may include growing a first epitaxy layer at a first side and a second side of a stack of gates and channels, applying a sacrificial layer on the first epitaxy layer, growing a second epitaxy layer on the sacrificial layer, removing the sacrificial layer, and depositing a metal layer on the first epitaxy layer and the second epitaxy layer at the first side of the stack of gates and channels.

Abstract: Integrated circuit devices including a via and methods of forming the same are provided. The methods may include forming a conductive wire structure on a substrate. The conductive wire structure may include a first insulating layer and a conductive wire stack in the first insulating layer, and the conductive wire stack may include a conductive wire and a mask layer stacked on the substrate. The method may also include forming a recess in the first insulating layer by removing the mask layer, the recess exposing the conductive wire, forming an etch stop layer and then a second insulating layer on the first insulating layer and in the recess of the first insulating layer, and forming a conductive via extending through the second insulating layer and the etch stop layer and contacting the conductive wire.