Abstract: A method of manufacturing a three-dimensional field-effect transistor including an upper field-effect transistor stacked on a lower field-effect transistor. The method includes epitaxially growing source/drain regions of the lower field-effect effect transistor, growing a sacrificial layer on an upper surface of the source/drain regions, and epitaxially growing source/drain regions of the upper field-effect transistor on the sacrificial layer. The sacrificial layer is a seed layer for the source/drain regions of the upper field-effect transistor. The method also includes selectively etching the sacrificial layer to form a gap between the source/drain regions of the lower field-effect transistor and the source/drain regions of the upper field-effect transistor, and depositing an oxide layer in the gap.

Abstract: An magnetoresistive random access memory (MRAM) device includes a magnetic tunnel junction, and a spin-orbit torque material. Based on a current applied to the spin-orbit torque material, the spin-orbit torque material generates spin polarization along one or multiple axes.

Abstract: Provided are systems, methods, and apparatuses for applying stress in transistors. In one or more examples, the systems, devices, and methods include depositing an epitaxial film on a surface between a first sidewall and a second sidewall of the transistor; depositing a dielectric over the epitaxial film and on the surface between the first sidewall and the second sidewall to increase stress in a silicon channel of the transistor; removing a polysilicon fin between the second sidewall and a third sidewall; and depositing a first metal between the second sidewall and the third sidewall based on removing the polysilicon fin.

Abstract: According to one or more embodiments of the present disclosure, a semiconductor device is described. The semiconductor device may include a substrate, a channel portion on the substrate between a source region and a drain region, and a gate on the channel. The channel portion may include a first portion extending in a first direction and at least one second portion protruding from the first portion in a second direction crossing the first portion.

Abstract: A field-effect transistor includes a substrate, a channel on the substrate including a stem including silicon extending in a vertical direction from the substrate and a number of prongs including silicon extending in a horizontal direction from the stem and spaced apart from each other along the vertical direction, an interfacial layer surrounding the stem and the prongs of the channel, a dielectric layer on the interfacial layer and surrounding the stem and the prongs of the channel, and a metal gate on the dielectric layer and surrounding the stem and the prongs of the channel.

Abstract: A method for manufacturing a semiconductor device according to one or more embodiments may include growing a first epitaxy layer at a first side and a second side of a stack of gates and channels, applying a sacrificial layer on the first epitaxy layer, growing a second epitaxy layer on the sacrificial layer, removing the sacrificial layer, and depositing a metal layer on the first epitaxy layer and the second epitaxy layer at the first side of the stack of gates and channels.

Abstract: Integrated circuit devices including a via and methods of forming the same are provided. The methods may include forming a conductive wire structure on a substrate. The conductive wire structure may include a first insulating layer and a conductive wire stack in the first insulating layer, and the conductive wire stack may include a conductive wire and a mask layer stacked on the substrate. The method may also include forming a recess in the first insulating layer by removing the mask layer, the recess exposing the conductive wire, forming an etch stop layer and then a second insulating layer on the first insulating layer and in the recess of the first insulating layer, and forming a conductive via extending through the second insulating layer and the etch stop layer and contacting the conductive wire.

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a lower source/drain region of a 1st polarity type connected to a lower channel structure; an upper source/drain region of a 2nd polarity type, connected to an upper channel structure, above the lower source/drain region; and a PN junction structure, between the lower source/drain region and the upper source/drain region, configured to electrically isolate the upper source/drain region from the lower source/drain region, wherein the PN junction structure includes a 1st region of the 1st polarity type and a 2nd region of the 2nd polarity type.

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a 1st lower source/drain region and a 2nd lower source/drain region connected to each other through a 1st lower channel structure controlled by a 1st gate structure; and a 1st upper source/drain region and a 2nd upper source/drain regions, respectively above the 1st lower source/drain region and the 2nd lower source/drain region, and connected to each other through a 1st upper channel structure controlled by the 1st gate structure, wherein the 2nd lower source/drain region and the 2nd upper source/drain region form a PN junction therebetween.

Abstract: A method and electronic device are provided. The electronic device includes a first dielectric layer; a metal patterned in the first dielectric layer; a second dielectric layer deposited on the first dielectric layer; and a metal via deposited in a channel in the second dielectric layer, the metal via being in contact with the patterned metal in the first dielectric layer. The channel is formed by removing at least a portion of a nanowall formed on the metal in the first dielectric layer.

Abstract: A method and electronic device are provided. The method includes patterning a metal in a first dielectric layer, depositing a first metal layer over the patterned metal, forming a nanowall under the first metal layer such that the nanowall is in contact with the patterned metal in the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, removing at least a portion of the nanowall, thereby forming a channel in the second dielectric layer, and depositing a metal via in the channel such that the metal via is in contact with the patterned metal in the first dielectric layer.

Abstract: Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.

Abstract: Described are low resistivity metal layers/films, such as low resistivity ruthenium (Ru) layers/films, and methods of forming low resistivity metal films. Ru layers/films with close-to-bulk resistivity can be prepared on substrates using Ru(CpEt)2 + O2 ALD, as well as a two-step ALD process using Ru(DMBD)(CO)3 + TBA (tertiary butyl amine) to nucleate the substrate and Ru(EtCp)2 + O2 to increase layer/film thickness. The Ru layer/films and methods of preparing Ru layers/films described herein may be suitable for use in barrierless via-fills, as well as at M0/M1 interconnect layers.

Abstract: Integrated circuit devices and methods of forming the integrated circuit device are provided. The methods may include providing a preliminary transistor stack including an upper sacrificial layer on a substrate, an upper active region between the substrate and the upper sacrificial layer, a lower sacrificial layer between the substrate and the upper active region, and a lower active region between the substrate and the lower sacrificial layer. The methods may further include forming lower source/drain regions on respective opposing side surfaces of the lower active region, forming a preliminary capping layer on a first lower source/drain region of the lower source/drain regions, the preliminary capping layer including a semiconductor material, converting the preliminary capping layer to a capping layer that includes an insulating material, and forming upper source/drain regions on respective opposing side surfaces of the upper active region.

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Abstract: Integrated circuit devices including a via and methods of forming the same are provided. The methods may include forming a conductive wire structure on a substrate. The conductive wire structure may include a first insulating layer and a conductive wire stack in the first insulating layer, and the conductive wire stack may include a conductive wire and a mask layer stacked on the substrate. The method may also include forming a recess in the first insulating layer by removing the mask layer, the recess exposing the conductive wire, forming an etch stop layer and then a second insulating layer on the first insulating layer and in the recess of the first insulating layer, and forming a conductive via extending through the second insulating layer and the etch stop layer and contacting the conductive wire.

Abstract: A method and electronic device are provided. The method includes patterning a metal in a first dielectric layer, depositing a first metal layer over the patterned metal, forming a nanowall under the first metal layer such that the nanowall is in contact with the patterned metal in the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, removing at least a portion of the nanowall, thereby forming a channel in the second dielectric layer, and depositing a metal via in the channel such that the metal via is in contact with the patterned metal in the first dielectric layer.

Abstract: A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a first conductive layer on a substrate and selectively forming a second insulating layer on the first insulating layer. The first insulating layer may include a recess, and the first conductive layer may be in the recess of the first insulating layer. The second insulating layer may include a first opening exposing a surface of the first conductive layer. The methods may also include forming a third insulating layer on the second insulating layer and the first conductive layer, forming a second opening extending through the third insulating layer and exposing the first conductive layer, and forming a second conductive layer in the second opening.

Abstract: A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.