Patents by Inventor Harsono Simka

Harsono Simka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090166867
    Abstract: Cu interconnect structures using a bottomless liner to reduce the copper interfacial electron scattering and lower the electrical resistance are described in this application. The interconnect structures comprise a nucleation layer and a liner layer that may be formed by an oxide or nitride. The bottom portion of the liner layer is removed to expose the nucleation layer. Since the liner is bottomless, the nucleation layer is exposed during Cu deposition and serves to catalyze copper nucleation and enable selective growth of copper near the bottom (where the nucleation layer is exposed), rather than near the liner sidewalls. Thus, copper may be selectively grown with a bottom-up fill behavior than can reduce or eliminate formation of voids. Other embodiments are described.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Harsono Simka, Sadasivan Shankar, Michael Haverty, Ramanan Chebiam, Florian Gstrein
  • Patent number: 7470617
    Abstract: In one embodiment, the present invention includes a method for depositing a barrier layer on a substrate having a trench, depositing a liner layer on the barrier layer that includes a surface oxide, electrolessly depositing a copper seed layer on the liner layer, where the surface oxide is reduced in-situ in an electroless bath, depositing a bulk metal layer on the copper seed layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventors: Ramanan Chebiam, Chin-Chang Cheng, Damian Whitney, Harsono Simka
  • Publication number: 20080213994
    Abstract: In one embodiment, the present invention includes a method for depositing a barrier layer on a substrate having a trench, depositing a liner layer on the barrier layer that includes a surface oxide, electrolessly depositing a copper seed layer on the liner layer, where the surface oxide is reduced in-situ in an electroless bath, depositing a bulk metal layer on the copper seed layer. Other embodiments are described and claimed.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 4, 2008
    Inventors: Ramanan Chebiam, Chin-Chang Cheng, Damian Whitney, Harsono Simka
  • Publication number: 20080194105
    Abstract: Organometallic precursors and methods for deposition on a substrate in seed/barrier applications are herein disclosed. In some embodiments, the organometallic precursor is a ruthenium-containing, tantalum-containing precursor or combination thereof and may be deposited by atomic layer deposition, chemical vapor deposition and/or physical vapor deposition.
    Type: Application
    Filed: February 14, 2007
    Publication date: August 14, 2008
    Inventors: Juan Dominguez, Adrien Lavoie, John Plombon, Joseph Han, Harsono Simka, David Thompson, John Peck
  • Publication number: 20070264816
    Abstract: A method for forming a metal interconnect comprises providing a dielectric layer on a substrate within a reaction chamber where the dielectric layer includes a trench, conformally depositing a barrier layer on the dielectric layer within the trench, conformally depositing a Cu—Al alloy layer on the barrier layer within the trench, depositing a copper layer to fill the trench, and planarizing the copper layer to form the metal interconnect. The Cu—Al alloy layer may be formed by sequential ALD or CVD deposition of an aluminum layer and a copper layer followed by an annealing process. Alternately, the Cu—Al alloy layer may be formed in-situ by co-pulsing the aluminum and copper precursors.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 15, 2007
    Inventors: Adrien Lavoie, Juan Dominguez, John Plombon, Joseph Han, Harsono Simka
  • Publication number: 20070202678
    Abstract: A method for carrying out a damascene process to form an interconnect comprises providing a semiconductor substrate having a trench etched into a dielectric layer, wherein the trench includes a barrier layer and an adhesion layer, depositing a copper seed layer onto the adhesion layer using an ALD process, depositing an iodine catalyst layer onto the copper seed layer using an ALD process, and depositing a copper layer onto the copper seed layer using an ALD process. The iodine catalyst layer causes the copper layer to fill the trench by way of a bottom-up fill mechanism. The trench fill is performed using a single ALD process, which minimizes the creation of voids and seams in the final copper interconnect.
    Type: Application
    Filed: February 28, 2006
    Publication date: August 30, 2007
    Inventors: John Plombon, Adrien Lavoie, Juan Dominguez, Joseph Han, Harsono Simka
  • Publication number: 20070194287
    Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.
    Type: Application
    Filed: February 22, 2006
    Publication date: August 23, 2007
    Inventors: Juane Dominguez, Adrien Lavoie, John Plombon, Joseph Han, Harsono Simka
  • Patent number: 7220671
    Abstract: Chemical phase deposition processes utilizing organometallic precursors to form thin films are herein described. The organometallic precursors may include a single metal center or multiple metal centers. The chemical phase deposition may be chemical vapor deposition (CVD), atomic layer deposition (ALD), or hybrid CVD and ALD. The use of these chemical phase deposition processes with the organometallic precursors allows for the conformal deposition of films within openings having widths of less than 100 nm and more particularly less than 50 nm to form thin films such as barrier layers, seed layers, and adhesion layers.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Harsono Simka, Juan Dominguez, Steven Johnston, Adrien Lavoie, Kevin O'Brien
  • Publication number: 20070099420
    Abstract: A method comprising introducing an organometallic precursor according to a first set of conditions in the presence of a substrate; introducing the organometallic precursor according to a different second set of conditions in the presence of the substrate; and forming a layer comprising a moiety of the organometallic precursor on the substrate according to an atomic layer deposition process. A system comprising a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor comprising a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures formed in a plurality of dielectric layers formed on the substrate and each of the plurality of interconnect structures separated from the plurality of dielectric layers by a barrier layer formed according to an atomic layer deposition process.
    Type: Application
    Filed: November 2, 2005
    Publication date: May 3, 2007
    Inventors: Juan Dominguez, Adrien Lavoie, Harsono Simka, John Plombon, David Thompson, John Peck
  • Publication number: 20060223300
    Abstract: Chemical phase deposition processes utilizing organometallic precursors to form thin films are herein described. The organometallic precursors may include a single metal center or multiple metal centers. The chemical phase deposition may be chemical vapor deposition (CVD), atomic layer deposition (ALD), or hybrid CVD and ALD. The use of these chemical phase deposition processes with the organometallic precursors allows for the conformal deposition of films within openings having widths of less than 100 nm and more particularly less than 50 nm to form thin films such as barrier layers, seed layers, and adhesion layers.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Inventors: Harsono Simka, Juan Dominguez, Steven Johnston, Adrien Lavoie, Kevin O'Brien
  • Publication number: 20060138087
    Abstract: A slurry for use in a chemical mechanical polishing process for planarizing copper-based metal structures on a substrate comprises an oxidizer, an organic complexing agent, surfactants, and a plurality of copper-based metal abrasive particles, wherein the copper in the copper-based metal is capable of dissolving into the slurry and forming copper ion complexes. During the chemical mechanical polishing process, the copper removal rate may be selectively increased by increasing the concentration of copper metal abrasive particles in the slurry, and the copper removal rate may be selectively decreased by decreasing the concentration of copper metal abrasive particles in the slurry.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 29, 2006
    Inventors: Harsono Simka, Sadasivan Shankar, Lei Jiang, Paul Fischer, Anne Miller, Kenneth Cadien
  • Publication number: 20050173241
    Abstract: An apparatus with a plating container with at least two anodes is described herein.
    Type: Application
    Filed: February 6, 2004
    Publication date: August 11, 2005
    Inventors: Radek Chalupa, Harsono Simka, Sadasivan Shankar, Daniel Zierath, Iouri Lantassov, Terry Buckley, Anand Durairajan