Abstract: The present invention provides a technology for using an STB in conjunction with various display panels that comprise different types of display devices. The present invention comprises a display panel (2), which includes a memory section (255) and a transmitter section (210). The memory section (255) stores identification information (ID information), which includes the information about the type of a device constituting the display panel (2) and/or the specifications for the display panel. The transmitter section (210) transmits the ID information stored in the memory section (255) to a signal processing apparatus (1).

Abstract: The present invention provides a movement correction frame count transformation apparatus for carrying out frame count transformation processing on a picture signal. In the apparatus, an input picture signal (S1) of interlaced scanning is converted into a signal (S2) of sequential scanning by an IP conversion unit (1). A movement detecting unit (3) detects movement detection signals (MD1 and MD2). A block unit movement vector searching unit (4) detects a block unit movement vector (BMV) by carrying out block matching processing. A movement vector correcting unit (5) carries out miniblock division processing to generate a movement vector (BV) if a movement correction error is equal to or greater than a threshold value. A pixel unit movement vector generating unit (6) generates a movement vector with a smallest error component between a frame signal of a current frame and a frame signal of an immediately preceding frame as a movement vector of a pixel.

Abstract: A video display device that allows the color temperature of the signals in white color attributes having high luminance and low chroma saturation to be corrected with high precision is provided together with the color temperature correction method for the same so as to visually obtain a desirable white color on display.

Abstract: A low-cost motion-compensated picture signal scan conversion circuit ensuring high picture quality is to be provided. The circuit has a motion-adaptive first interpolation signal generator; a second motion-compensated interpolation signal generator; a motion vector detector; and a setting unit for checking the reliability of motion compensation by comparing signals from the second interpolation signal generator with signals on interlaced scanning lines, and setting the selection of signals from the first and second interpolation signal generators, wherein interlaced scanned signals are converted into progressive scanned signals by setting the threshold so that the threshold become smaller with an increase in the number of re-searched blocks in the detection of motion vectors.

Abstract: A gamma correction circuit includes a node level setting unit set predetermined level values of video signals from outside, in a case where encoded M-bit (where M is an arbitrary integer) video signals being represented by using predetermined number of sections and the level values of the video signals corresponding to 2n+1 number of nodes (where n is an arbitrary integer) associated with the sections on which the node are specified, and a gamma correction unit for executing gamma correction for the M-bit video signal in accordance with the level values of the nodes set in the node level setting unit, thereby the gamma correction circuit executes gamma correction on various types of display devices.

Abstract: A noise reduction signal processing apparatus for reducing noises accurately, such as for use in a display apparatus for displaying a video signal, has a median filter (40) which receives the video signal, and which executes a filter processing on the inputted video signal and outputs a reference signal; a subtracter (50) which is connected with the median filter (40), and which outputs a difference signal that indicates a difference between a reference signal outputted from the median filter (40) and the video signal; a minimum value detection circuit (70) which outputs the difference signal from the subtracter (50) or a limitation value, whichever is smaller, as a minimum value signal; and an adder (35) which adds a noise reduction signal obtained on the basis of the minimum value signal output from the minimum value detection circuit (70) and the video signal.

Abstract: In order to carry out format conversion or scaling processing of picture signal by a memory having a small capacity, picture signals of interlace scanning are converted into picture signals of progressive scanning by interpolation by using an IP convertor 1 and a multiple scan convertor 3, a scaling processing of expansion and compression in the horizontal direction is firstly performed by using a horizontal scaling unit 5, processing of expansion, compression, frame rate conversion, synchronization and the like are secondly performed by using a vertical scaling unit 6 and commonly using memories used in scaling processing in the vertical direction and finally, color space conversion or inverse gamma processing is performed by using a picture quality improving unit 8 thereby converting the picture signals into picture signals S6 having a predetermined format.

Abstract: A video signal processor which includes a circuit for converting the number of lines in a digitized video signal, a circuit for generating a display dot clock, a circuit for outputting analog pixel data subjected to a line number conversion and having a frequency different from that of the display dot clock, and a circuit for smoothing the analog pixel data; and in which a frequency fck of the display dot clock, an output frequency frk of the analog pixel data and a frequency fho of the horizontal synchronization signal satisfies an equation;frck/N=fck/M=fhowhere M and N are natural numbers satisfying M.noteq.N.

Abstract: To provide an image which is matched with an aspect ratio of a screen of a display unit by compressing and enlarging the whole of the image to a desired size. A video signal is sequentially written into a field memory in response to a write clock from an input terminal. A clock generating circuit supplies the field memory with a read clock having a frequency which is about 4/3 times as high as that of the write clock. A vertical enlargement control circuit reads a video signal from the field memory with a line period corresponding to a magnification factor and inhibits writing to a one-line memory with the same period to provide a line delayed output for an output signal from the field memory. A vertical interpolating circuit generates a scanning line signal by an interpolation operation in accordance with a control signal from the vertical enlargement control circuit.

Abstract: A wide-screen television receiver capable of converting a TV signal of a non-aspect ratio into a signal of a wide aspect ratio which can be displayed on a wide screen of the wide aspect ratio and previously visually informing the user of what part of the image of the non-aspect ratio TV signal is converted in its aspect ratio and displayed on the wide screen. The receiver includes the interpolation scan speed conversion circuit, the mode setting circuit, the aspect ratio converting circuit, the wide cursor adding circuit and the wide display. The interpolation scan speed conversion circuit makes a series of processes such as Y/C separation and scan line interpolation for the input video signal supplied via the input terminal. The aspect ratio converting circuit compresses the video signal from the interpolation scan speed conversion circuit in the horizontal direction by use of a memory. The magnification processing circuit is provided after the aspect ratio converting circuit.

Abstract: A video signal processing circuit is provided to display an image of a standard television signal on a display unit with a 6:9 aspect ratio by enlarging an image of a video signal in the horizontal and vertical directions by a magnification factor which depends on the feature of the standard television signal. The processing circuit includes a first memory circuit which reads out the stored video signal in response to a read clock different from the write clock and generated by a stable frequency source so that the image of the video signal is expanded in the vertical direction, a second memory circuit which implements time-base compression for the output of the first memory circuit and thereafter expands the signal, a spatial filter which implements filtering for the output of the second memory circuit, an enlargement control circuit which control the above-mentioned circuits, and a synchronizing processing circuit.