Patents by Inventor Haruki Toda

Haruki Toda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10022279
    Abstract: Provided is a disposable urine-absorption pad with which production costs are reduced, and with which a function for inhibiting the occurrence or aggravation of bedsores is imparted by facilitating relative movement of a skin-contact sheet in a back-and-forth direction with respect to a pad main body. This urine-absorption pad includes: an outer surface sheet; an absorption body; an inner surface sheet; a left side sheet; a right side sheet; an overlap sheet; and a low friction member. The overlap sheet is provided to a gluteal region. A right side edge of the overlap sheet is joined to a left side part of the right side sheet. A left side edge of the overlap sheet is joined to a right side part of the left side sheet. The low friction member is provided between the overlap sheet and the inner surface sheet.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: July 17, 2018
    Assignee: Unicharm Corporation
    Inventors: Haruki Toda, Takahito Nagai
  • Patent number: 9700464
    Abstract: An absorbent article which has in a longitudinal direction from the front side to the rear side a front waist region, a rear waist region and a crotch region located between the front and rear waist regions. An absorbent sheet is provided between a topsheet and a second sheet which includes at least one liquid-pervious sheet having sandwiched therein an absorbent polymer that is present between a topsheet and a second sheet. The second sheet has a higher liquid diffusibility than the topsheet, the topsheet, a backsheet, an absorption body and the second sheet are disposed across the front waist region, the crotch region and the rear waist region, and the absorbent sheet is disposed in at least a part of the rear waist region.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: July 11, 2017
    Assignee: Unicharm Corporation
    Inventors: Haruki Toda, Kaiyou Nakajima
  • Patent number: 9691474
    Abstract: A memory system according to the embodiment comprises a cell array of plural cells having three or more settable physical quantity levels and operative to store a code composed of symbols expressed by elements in a finite field Zp (p is a prime), wherein a set of two cells is defined as a pair cell and a combination of physical quantity levels of the two cells contained in the pair cell is defined as a pair cell level, wherein the pair cell uses a pair cell level of plural pair cell levels, which maximizes or minimizes a physical quantity level of one cell contained in the pair cell, to assign elements in the Zp to the pair cell levels, thereby storing symbols of the code.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: June 27, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki Toda
  • Publication number: 20170135869
    Abstract: Provided is an absorbent article in which the shape of projections formed in a predetermined region of a topsheet can be maintained. In this absorbent article: a nonwoven fabric that has a skin-side surface having projections formed thereon is used as a topsheet; and an absorbent body has formed therein a through hole that penetrates the absorbent body in the thickness direction.
    Type: Application
    Filed: June 11, 2015
    Publication date: May 18, 2017
    Applicant: UNICHARM CORPORATION
    Inventors: Ayako MORIYA, Haruki TODA
  • Patent number: 9520188
    Abstract: A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: December 13, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki Toda
  • Publication number: 20160225441
    Abstract: A memory system according to the embodiment comprises a cell array of plural cells having three or more settable physical quantity levels and operative to store a code composed of symbols expressed by elements in a finite field Zp (p is a prime), wherein a set of two cells is defined as a pair cell and a combination of physical quantity levels of the two cells contained in the pair cell is defined as a pair cell level, wherein the pair cell uses a pair cell level of plural pair cell levels, which maximizes or minimizes a physical quantity level of one cell contained in the pair cell, to assign elements in the Zp to the pair cell levels, thereby storing symbols of the code.
    Type: Application
    Filed: April 6, 2016
    Publication date: August 4, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • Patent number: 9368197
    Abstract: A memory system according to the embodiment comprises a cell array of plural cells having three or more settable physical quantity levels and operative to store a code composed of symbols expressed by elements in a finite field Zp (p is a prime), wherein a set of two cells is defined as a pair cell and a combination of physical quantity levels of the two cells contained in the pair cell is defined as a pair cell level, wherein the pair cell uses a pair cell level of plural pair cell levels, which maximizes or minimizes a physical quantity level of one cell contained in the pair cell, to assign elements in the Zp to the pair cell levels, thereby storing symbols of the code.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: June 14, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki Toda
  • Patent number: 9336085
    Abstract: A memory system according to the embodiment comprises a memory device including plural memory cells capable of storing d bits of data and operative to read/write data at every page; and a memory controller operative to control the memory device. The memory controller includes a page buffer operative to hold page data to be read from/written in a page of the memory device and send/receive the page data to/from the memory device, a data processing unit operative to detect and correct an error in the page data by processing target data in a finite field Zp modulo p generated based on the page data (p is a prime that satisfies 2<p<2d), and a mapping unit operative to execute mapping of the target data from the data processing unit as page data within the page buffer.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: May 10, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki Toda
  • Publication number: 20160086661
    Abstract: A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.
    Type: Application
    Filed: November 3, 2015
    Publication date: March 24, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • Patent number: 9271882
    Abstract: An absorbent article configured to ensure that even when the excreted urine diffuses by running down the wearer's skin, the skin is prevented from remaining wetted. In the absorbent article of the present invention, when an artificial urine is dropped and absorbed in the urination region of the crotch region, where an absorbent sheet is not disposed, the return amount of the artificial urine in the buttock region of the rear waist region, where an absorbent sheet is disposed, takes a value of 200 times less than the return amount of the artificial urine in the urination region; and the return amount of the artificial urine in the buttock region when the artificial urine is dropped and absorbed in the buttock region takes a value of 0.7 or less of the return amount of the artificial urine in the urination region when the artificial urine is dropped and absorbed in the urination region.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: March 1, 2016
    Assignee: Unicharm Corporation
    Inventors: Kaiyo Nakajima, Haruki Toda
  • Patent number: 9245621
    Abstract: A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: January 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jun Deguchi, Haruki Toda
  • Publication number: 20160012884
    Abstract: A memory system according to the embodiment comprises a memory cell having plural transitionable physical states, the plural physical states including a certain physical state defined as a first physical state, and a physical state held in the memory cell defined as a second physical state, and the memory cell storing plural different data in accordance with differences in transition time from the second physical state to the first physical state.
    Type: Application
    Filed: September 9, 2014
    Publication date: January 14, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Haruki TODA
  • Publication number: 20150366725
    Abstract: Provided is a disposable urine-absorption pad with which production costs are reduced, and with which a function for inhibiting the occurrence or aggravation of bedsores is imparted by facilitating relative movement of a skin-contact sheet in a back-and-forth direction with respect to a pad main body. This urine-absorption pad includes: an outer surface sheet; an absorption body; an inner surface sheet; a left side sheet; a right side sheet; an overlap sheet; and a low friction member. The overlap sheet is provided to a gluteal region. A right side edge of the overlap sheet is joined to a left side part of the right side sheet. A left side edge of the overlap sheet is joined to a right side part of the left side sheet. The low friction member is provided between the overlap sheet and the inner surface sheet.
    Type: Application
    Filed: January 15, 2014
    Publication date: December 24, 2015
    Inventors: Haruki Toda, Takahito Nagai
  • Patent number: 9214226
    Abstract: A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: December 15, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki Toda
  • Patent number: 9190146
    Abstract: A memory system according to the embodiment comprises a cell array of unit cell arrays each including memory cells; and an access circuit, wherein the memory cell changes from a first resistance state to a second resistance state on application of a first polarity voltage, and changes from the second resistance state to the first resistance state on application of a second polarity voltage, the access circuit provides the first and second lines connected to an access-targeted memory cell with access potentials, and brings at least one of the first and second lines connected to an access-untargeted memory cell into a floating state to make access to the access-targeted memory cell, the unit cell array includes first spare lines to provide redundancy for the first lines, and an alignment of the first lines includes a certain number of the first spare lines arranged in a certain cycle.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: November 17, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki Toda
  • Patent number: 9171598
    Abstract: A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different physical states; and an access circuit operative to make access to the memory cell via the first line and the second line, wherein the access circuit, on writing data in the access cell, uses a non-access-side first line driver to electrically connect a non-access first line adjacent to an access first line to a first potential power supply via a diode-connected transistor.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: October 27, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki Toda
  • Publication number: 20150279456
    Abstract: According to an embodiment, a semiconductor memory device has: a memory cell array formed by stacking through insulation layers a plurality of memory mats which each have a plurality of first lines, a plurality of second lines and a plurality of resistance varying memory cells provided at intersection portions of the pluralities of first lines and second lines; and an accessing circuit which applies voltages to the memory cell array. A number of the first lines included in the memory mat is greater than a number of the second lines. When the accessing circuit accesses the selected memory cell, the accessing circuit selects a plurality of first lines and a second line connected to selected memory cells to which the accessing circuit needs to be connected and judges data stored in the selected memory cells according to currents flowing to the selected memory cells.
    Type: Application
    Filed: June 11, 2015
    Publication date: October 1, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • Patent number: 9135991
    Abstract: A semiconductor memory device according to the embodiment comprises memory cells each having asymmetrical voltage-current characteristics, wherein the memory cell has a first state, and a second state and a third state of higher resistances than that in the first state, wherein the memory cell, (1) in the second state, makes a transition to the first state on application of a first voltage of the first polarity, (2) in the first state, makes a transition to the second state on application of a second voltage of the second polarity, (3) in the first state, makes a transition to the third state on application of a third voltage of the second polarity (the third voltage<the second voltage), and (4) in the third state, makes a transition to the first state on application of a fourth voltage of the first polarity (the fourth voltage<the first voltage).
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: September 15, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki Toda
  • Patent number: 9111611
    Abstract: A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different resistance states; and an access circuit operative to execute a write sequence of changing the resistance state for writing data in the memory cell, wherein the access circuit, on the write sequence, executes a first step of changing all memory cells provided at the intersections of access first lines and the access and fault second lines to the high resistance state, and a second step of changing all or part of access cells connected to the access second line to the low resistance state.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: August 18, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki Toda
  • Publication number: 20150213886
    Abstract: A memory system according to the embodiment comprises a cell array of plural cells having three or more settable physical quantity levels and operative to store a code composed of symbols expressed by elements in a finite field Zp (p is a prime), wherein a set of two cells is defined as a pair cell and a combination of physical quantity levels of the two cells contained in the pair cell is defined as a pair cell level, wherein the pair cell uses a pair cell level of plural pair cell levels, which maximizes or minimizes a physical quantity level of one cell contained in the pair cell, to assign elements in the Zp to the pair cell levels, thereby storing symbols of the code.
    Type: Application
    Filed: March 11, 2014
    Publication date: July 30, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA