Patents by Inventor Haruki Toda

Haruki Toda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RESISTANCE CHANGE MEMORY DEVICE
    Publication number: 20120008372
    Abstract: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.
    Type: Application
    Filed: September 20, 2011
    Publication date: January 12, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Haruki Toda, Hirofumi Inoue, Hiroto Nakai
  • RESISTANCE CHANGE MEMORY DEVICE
    Publication number: 20120002458
    Abstract: A resistance change memory device includes: a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting a selected word line and the reference bit line at the same time; and a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the selected bit line and the reference cell on the reference bit line.
    Type: Application
    Filed: September 13, 2011
    Publication date: January 5, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • PHASE CHANGE MEMORY DEVICE
    Publication number: 20110305076
    Abstract: A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.
    Type: Application
    Filed: August 25, 2011
    Publication date: December 15, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Haruki TODA
  • RESISTANCE CHANGE MEMORY DEVICE
    Publication number: 20110267872
    Abstract: A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path of the memory cell as to serve for stabilizing the state change of the memory cell passively.
    Type: Application
    Filed: July 13, 2011
    Publication date: November 3, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • Resistance change memory device
    Patent number: 8031508
    Abstract: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: October 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Haruki Toda, Hirofumi Inoue, Hiroto Nakai
  • MEMORY SYSTEM AND METHOD OF DATA WRITING AND READING IN MEMORY SYSTEMS
    Publication number: 20110239091
    Abstract: A memory system according to the embodiment comprises a p-adic number converter unit operative to convert ?-digit, h-bit symbols to a k-digit, p-adic data word (p is a prime of 3 or more); an encoder unit operative to generate, from the p-adic data word, a code C composed of a residual field Zp of the prime p; a memory unit operative to store the code C as write data; an error correcting unit operative to apply an operation using a syndrome S generated from read data Y for error correcting the read data Y to regenerate the code C; a decoder unit operative to reverse-convert the code C to regenerate the p-adic data word; and a binary converter unit operative to convert the data word to a binary number to regenerate the binary data D.
    Type: Application
    Filed: January 21, 2011
    Publication date: September 29, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Resistance change memory device
    Patent number: 8023313
    Abstract: A resistance change memory device includes a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting a selected word line and the reference bit line at the same time; and a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the selected bit line and the reference cell on the reference bit line.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: September 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Phase change memory device
    Patent number: 8022381
    Abstract: A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: September 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • PHASE-CHANGE MEMORY DEVICE
    Publication number: 20110205790
    Abstract: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.
    Type: Application
    Filed: May 3, 2011
    Publication date: August 25, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • Resistance change memory device
    Patent number: 8004873
    Abstract: A resistance change memory device including a memory cell array with first wirings, second wirings, and memory cells, the memory cell including a diode and a variable resistance element, anode of diodes being located on the first wiring side, wherein the memory cell array is sequentially set in the following three states after power-on: a waiting state defined by that both the first and second wirings are set at a first voltage; a standby state defined by that the first wirings are kept at the first voltage and the second wirings are set at a second voltage higher than the first voltage; and an access state defined by that a selected first wiring and a selected second wiring are set at a third voltage higher than the first voltage and the first voltage, respectively.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: August 23, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • ERROR DETECTION AND CORRECTION SYSTEM
    Publication number: 20110202815
    Abstract: An error detection and correction system in accordance with an embodiment comprises: an encoding unit; a syndrome calculating unit; a syndrome element calculating unit; an error search unit; and an error correction unit, read and write of a memory cell array being assumed to be performed concurrently for m bits, and error detection and correction being assumed to be performed in data units of M bits (where M is an integer multiple of m), and an encoding unit and a syndrome calculating unit sharing a time-division decoder for performing data bit selection according to respective tables of check bit generation and syndrome generation, the time-division decoder being operative to repeat multiple cycles of m bit concurrent data input.
    Type: Application
    Filed: January 21, 2011
    Publication date: August 18, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • Semiconductor memory device
    Patent number: 8001448
    Abstract: A semiconductor memory device including an error detecting and correcting system, wherein the error detecting and correcting system includes a 3EC system configured to be able to detect and correct 3-bit errors, and wherein the 3EC system is configured to search errors in such a manner that 3-degree error searching equation is divided into a first part containing only unknown numbers and a second part calculative with syndromes via variable transformation by use of two or more parameters, and previously nominated solution indexes collected in a table and syndrome indexes are compared to each other.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: August 16, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Resistance change memory device with stabilizing circuit coupled in series with selected resistance change memory cell
    Patent number: 7995372
    Abstract: A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path of the memory cell as to serve for stabilizing the state change of the memory cell passively.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Phase-change memory device that stores information in a non-volatile manner by changing states of a memory material
    Patent number: 7989789
    Abstract: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: August 2, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Resistance change memory device for storing information in a non-volatile manner by changing resistance of memory material
    Patent number: 7989794
    Abstract: A resistance change memory device including a substrate, first and second wiring lines formed above the substrate to be insulated from each other, and memory cells disposed between the first and second wiring lines, wherein the memory cell includes: a variable resistance element for storing as information a resistance value; and a Schottky diode connected in series to the variable resistance element. The variable resistance element has: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of which serves as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: August 2, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Haruki Toda, Koichi Kubo
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20110185261
    Abstract: A memory device includes an error detection and correction system with an error correcting code over GF(2n), wherein the system has an operation circuit configured to execute addition/subtraction with modulo 2n?1, and wherein the operation circuit has a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where, M and N are integers which are prime with each other as being obtained by factorizing 2n?1), and wherein the first and second operation parts perform addition/subtraction in parallel to output an operation result of the addition/subtraction with modulo 2n?1.
    Type: Application
    Filed: April 5, 2011
    Publication date: July 28, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • Memory device with an ECC system
    Patent number: 7962838
    Abstract: A memory device has an error detection and correction system constructed on a Galois finite field. The error detection and correction system includes calculation circuits for calculating the finite field elements based on syndromes obtained from read data and searching error locations, the calculation circuits having common circuits, which are used in a time-sharing mode under the control of internal clocks.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: June 14, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Semiconductor memory device
    Patent number: 7941733
    Abstract: A memory device includes an error detection and correction system with an error correcting code over GF(2n) wherein the system has an operation circuit configured to execute addition/subtraction with modulo 2n?1, and wherein the operation circuit has a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where, M and N are integers which are prime with each other as being obtained by factorizing 2n?1), and wherein the first and second operation parts perform addition/subtraction in parallel to output an operation result of the addition/subtraction with modulo 2n?1.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: May 10, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • PHASE CHANGE MEMORY DEVICE
    Publication number: 20110080778
    Abstract: A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.
    Type: Application
    Filed: December 13, 2010
    Publication date: April 7, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • RESISTANCE CHANGE MEMORY DEVICE
    Publication number: 20110051492
    Abstract: A resistance change memory device including: a cell array with memory cells arranged therein, the memory cell storing a resistance state as data in a non-volatile manner; a write buffer configured to supply voltage and current to a selected memory cell in accordance with data to be written in it; and a write control circuit configured to make a part of current supplied to the selected memory cell flow out in accordance with the selected memory cell's state change in a write mode.
    Type: Application
    Filed: October 26, 2009
    Publication date: March 3, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA