Patents by Inventor Haruo Hori

Haruo Hori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10449144
    Abstract: The present invention provides a cancer vaccine composition for transdermal administration for inducing cellular immunity, comprising (i) a WT1 peptide and/or a modified WT1 peptide; and (ii) a cellular immunity induction promoter. The composition efficiently induces cellular immunity against a cancer in a subject.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: October 22, 2019
    Assignees: NITTO DENKO CORPORATION, OSAKA UNIVERSITY
    Inventors: Katsuyuki Okubo, Yoshiki Maeda, Arimichi Okazaki, Daisuke Asari, Takuya Shishido, Mitsuhiko Hori, Haruo Sugiyama
  • Patent number: 7215531
    Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: May 8, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Haruo Hori, Takanori Kondo
  • Patent number: 6909593
    Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: June 21, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Kuroda, Masaaki Taniguchi, Yasuyuki Naito, Haruo Hori, Takanori Kondo
  • Publication number: 20040223289
    Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.
    Type: Application
    Filed: June 17, 2004
    Publication date: November 11, 2004
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Kuroda, Masaaki Taniguchi, Yasuyuki Naito, Haruo Hori, Takanori Kondo
  • Patent number: 6771484
    Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: August 3, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Kuroda, Masaaki Taniguchi, Yasuyuki Naito, Haruo Hori, Takanori Kondo
  • Publication number: 20040140553
    Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.
    Type: Application
    Filed: January 8, 2004
    Publication date: July 22, 2004
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Haruo Hori, Takanori Kondo
  • Patent number: 6721153
    Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: April 13, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Haruo Hori, Takanori Kondo
  • Patent number: 6678145
    Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: January 13, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Haruo Hori, Takanori Kondo
  • Publication number: 20030198006
    Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.
    Type: Application
    Filed: May 22, 2003
    Publication date: October 23, 2003
    Applicant: Murata Manufacturing Co., Ltd
    Inventors: Yoichi Kuroda, Masaaki Taniguchi, Yasuyuki Naito, Haruo Hori, Takanori Kondo
  • Patent number: 6606237
    Abstract: A multilayer capacitor is constructed to minimize equivalent series inductance (ESL) and to achieve large capacitance. The capacitor includes first and second main go surface terminal electrodes provided on a first main surface of the main body of the multilayer capacitor. First and second side surface terminal electrodes are disposed on four side surfaces of the main body. The main body is divided into a low ESL section of the first main-surface side and a high capacitance section of the second main-surface side. In the low ESL section, in addition to first and second low ESL internal electrodes, a first conductive via-hole electrically connecting the first low ESL internal electrode to the first main surface terminal electrode and a second conductive via-hole electrically connecting the second low ESL internal electrode to the second main surface terminal electrode are provided.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: August 12, 2003
    Assignees: Murata Manufacturing Co., Ltd., Intel Corporation
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Haruo Hori, David G. Figueroa, Jorge P. Rodriguez, Nicholas R. Watts, Nicholas L. Holmberg, Takashi Hioki
  • Publication number: 20030142460
    Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.
    Type: Application
    Filed: October 23, 2001
    Publication date: July 31, 2003
    Applicant: Murata Manufacturing Co. Ltd.
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Haruo Hori, Takanori Kondo
  • Patent number: 6594136
    Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: July 15, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Kuroda, Masaaki Taniguchi, Yasuyuki Naito, Haruo Hori, Takanori Kondo
  • Patent number: 6556420
    Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: April 29, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Haruo Hori, Takanori Kondo
  • Publication number: 20020191366
    Abstract: An apparatus is provided for packaging a laminated capacitor made to have a low ESL value and is used for a decoupling capacitor to be connected to a power supply circuit for a MPU chip providing a MPU. The laminated capacitor is accommodated within a cavity provided on a wiring board. The capacitor includes a plurality of first external terminal electrodes connected to first internal electrodes via a plurality of first feedthrough conductors and a plurality of second external terminal electrodes connected to second internal electrodes via a plurality of second feedthrough conductors. The first external terminal electrodes provided on a first major surface of a capacitor body are connected to via-hole conductors at the hot side for the power source within a substrate, and the second external terminal electrodes provided on first and second major surfaces are connected to grounding via-hole conductors and a mother board within the substrate.
    Type: Application
    Filed: March 27, 2002
    Publication date: December 19, 2002
    Applicant: Murata Manufacturing Co. Ltd.
    Inventors: Yasuyuki Naito, Masaki Taniguchi, Yoichi Kuroda, Haruo Hori, Takanori Kondo
  • Patent number: 6407904
    Abstract: A multi-layer capacitor is constructed to minimize equivalent series inductance, increase resonance frequency, reduce the size of the capacitor and greatly improve the ease of mounting of the capacitor. A dimension in a length direction and a dimension in a width direction of a capacitor body are substantially equal, and a pattern of opposing first and second internal electrodes is substantially square. First lead-out portions of the first internal electrode and second lead-out portions of the second internal electrode are extended onto two side surfaces and two end surfaces. First external electrode terminals connected to the first lead-out portions and second external electrode terminals connected to the second lead-out portions are arranged so that they alternate adjacently and are arranged such that oppositely disposed external electrode terminals have opposite polarities.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: June 18, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Kuroda, Yasuyuki Naito, Masaaki Taniguchi, Haruo Hori, Takanori Kondo, Michihiro Murata, Yoshitaka Tanino
  • Publication number: 20020071238
    Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.
    Type: Application
    Filed: February 12, 2002
    Publication date: June 13, 2002
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Kuroda, Masaaki Taniguchi, Yasuyuki Naito, Haruo Hori, Takanori Kondo
  • Patent number: 6370010
    Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: April 9, 2002
    Assignee: Murata Manufacturing Co., LTD
    Inventors: Yoichi Kuroda, Masaaki Taniguchi, Yasuyuki Naito, Haruo Hori, Takanori Kondo
  • Patent number: 6351369
    Abstract: A multi-layer capacitor achieves significant reduction in equivalent series inductance (ESL) and includes first inner electrodes and second inner electrodes opposing each other, first feed-through conductors and second feed-through conductors, and first outer terminal electrodes and second outer terminal electrodes. The first feed-through conductors electrically connect the first inner electrodes and the first outer terminal electrodes, and the second feed-through conductors electrically connect the second inner electrodes and the second outer terminal electrodes. The first and second feed-through conductors are arranged such that the feed-through conductors mutually cancel magnetic fields induced by current flowing through the first and second inner electrodes. Furthermore, when an alignment pitch of the first and second feed-through conductors is indicated by P and the total number of the first and second feed-through conductors is indicated by N, an arrangement is set such that a ratio of P/N is about 0.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: February 26, 2002
    Assignee: Murata Manufacturing Co., LTD
    Inventors: Yoichi Kuroda, Masaaki Taniguchi, Yasuyuki Naito, Haruo Hori, Takanori Kondo
  • Patent number: 6344961
    Abstract: A multi-layer capacitor is constructed to minimize equivalent series inductance (ESL) and includes first inner electrodes and second inner electrodes disposed opposite to each other. The first inner electrodes are electrically connected to a first outer terminal electrode via a first feed-through conductor and the second inner electrodes are electrically connected to a second outer terminal electrode via a second feed-through conductor. The first and second feed-through conductors are arranged in such a manner that magnetic fields induced by current flowing through the inner electrodes are cancelled. In addition, some of these feed-through conductors are arranged to define first and second peripheral feed-through conductors connected to the first and second inner electrodes at each periphery of the first and second inner electrodes.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: February 5, 2002
    Assignee: Murata Manufacturing Co., LTD
    Inventors: Yasuyuki Naito, Masaaki Taniguchi, Yoichi Kuroda, Haruo Hori, Takanori Kondo
  • Patent number: 6331930
    Abstract: A multilayer capacitor is constructed and arranged to significantly reduce an equivalent serial inductance (ESL) and includes a capacitor body in which first and second inner electrodes extend, respectively, so as to connect first and second end surfaces and first and second side surfaces. First and second end surface terminal electrodes are provided on the first and second end surfaces. Also, first and second side surface terminal electrodes are provided on the first and second side surfaces, respectively. The widthwise dimension of the capacitor body is within a range of about 0.9 to about 1.1 times of the lengthwise dimension. Also, when a represents a lengthwise dimension and a widthwise dimension of the capacitor body, and b represents widths of the first inner electrodes and the second inner electrodes, it is preferable that a and b are determined so as to have the relationship of: 0.45≦b/a≦0.90.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: December 18, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Kuroda, Yasuyuki Naito, Haruo Hori, Takanori Kondo, Kyoshin Asakura