Abstract: An integrated circuit device includes first to Nth memory blocks disposed along a first direction, a power supply circuit, and a data driver disposed in a second direction with respect to the first to Nth memory blocks. The power supply circuit includes an analog reference power supply voltage output circuit that outputs an analog reference power supply voltage. The analog reference power supply voltage output circuit is disposed between an Mth memory block and an (M+1)th memory block among the first to Nth memory blocks. An analog reference power supply line is provided in an area of the data driver along the first direction.

Abstract: A rolling device in which rust development or damage on a raceway surface or rolling surface is hard to occur even if water and the like intrude is provided. A self-aligning roller bearing comprises an inner ring 1, an outer ring 2, and a plurality of rolling elements 3 disposed rotatably between a raceway surface 1a of the inner ring 1 and a raceway surface 2a of the outer ring 2. At least any one of the inner ring 1, the outer ring 2, and the rolling elements 3 is provided with a metal coating formed by shot peening of a powder of metal less noble than iron at least on a part of its surface.

Abstract: A D/A conversion circuit includes a first D/A converter and a second D/A converter that respectively output a first voltage and a second voltage. An ith two-input selector among a plurality of input selectors of the first D/A converter selects a (4i+1)th input voltage or a (4i+3)th input voltage based on input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage. An ith three-input selector among a plurality of three-input selectors of the second D/A converter selects a 4ith input voltage, a (4i+2)th input voltage, or a (4i+4)th input voltage based on the input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage.

Abstract: A driver circuit for driving source lines of an electro-optical device includes first and second source short-circuit circuits that respectively short-circuit first and second source lines and a source short-circuit node, a source charge storage short-circuit circuit that short-circuits a source charge storage node connected with one end of a source capacitor and the source short-circuit node, a voltage setting circuit that supplies a given voltage to the source charge storage node, and a node short-circuit circuit that short-circuits a common electrode voltage output node and the source short-circuit node, a voltage output to a common electrode of the electro-optical device provided opposite to a pixel electrode through an electro-optical element being applied to the common electrode voltage output node.

Abstract: A display driver includes a common electrode charge storage switch provided between a first capacitor element connection node to which one end of a first capacitor element can be connected and a common electrode voltage output node to which a voltage of a common electrode opposite to a pixel electrode of an electro-optical device through an electro-optical material is supplied, a source charge storage switch provided between a second capacitor element connection node to which one end of a second capacitor element can be connected and a source voltage output node to which a voltage of a source line of the electro-optical device is supplied, and a node short circuit switch provided between the common electrode voltage output node and the source voltage output node.

Abstract: A rolling device in which rust development or damage on a raceway surface or rolling surface is hard to occur even if water and the like intrude is provided. A self-aligning roller bearing comprises an inner ring 1, an outer ring 2, and a plurality of rolling elements 3 disposed rotatably between a raceway surface 1a of the inner ring 1 and a raceway surface 2a of the outer ring 2. At least any one of the inner ring 1, the outer ring 2, and the rolling elements 3 is provided with a metal coating formed by shot peening of a powder of metal less noble than iron at least on a part of its surface.

Abstract: A booster circuit including first to Mth power supply lines (M is an integer larger than 3) and first and second charge-pump circuits. Each of the charge-pump circuit has first to (M?2)th boost capacitors, wherein the jth boost capacitor (1?j?M?2, j is an integer) is connected between the jth power supply line and the (j+1)th power supply line in a first period and is connected between the (j+1)th power supply line and the (j+2)th power supply line in a second period subsequent to the first period. Each of the charge-pump circuits generates a boosted voltage by a charge-pump operation in different phases.

Abstract: An integrated circuit device includes first to Nth data driver blocks that are disposed along a first direction. Each of the first to Nth data driver blocks includes first to Mth sub-driver blocks. Each of the sub-driver blocks includes a D/A conversion circuit that receives image data and D/A-converts the image data, and first to Lth data line driver circuits that are disposed along the first direction in a second direction with respect to the D/A conversion circuit and share the D/A conversion circuit.

Abstract: An integrated circuit device includes first to Nth memory blocks disposed along a first direction, a power supply circuit, and a data driver disposed in a second direction with respect to the first to Nth memory blocks. The power supply circuit includes an analog reference power supply voltage output circuit that outputs an analog reference power supply voltage. The analog reference power supply voltage output circuit is disposed between an Mth memory block and an (M+1)th memory block among the first to Nth memory blocks.

Abstract: An integrated circuit device includes first to Nth memory blocks that are disposed along a first direction, and first to Nth data driver blocks that are disposed along the first direction in a second direction with respect to the first to Nth memory blocks. A Jth memory block among the first to Nth memory blocks dot-sequentially reads subpixel image data and outputs the subpixel image data to a corresponding Jth data driver block among the first to Nth data driver blocks, the subpixel image data being image data corresponding to at least one subpixel. The Jth data driver block receives the subpixel image data from the Jth memory block, and outputs a data signal corresponding to the subpixel image data.

Abstract: A first circuit is connected with the first and second power supply lines and a boost power supply line, and outputs a voltage obtained by multiplying the voltage between the first and second power supply lines M times (M is a positive integer), between the first power supply line and the boost power supply line. A second circuit is connected with the first power supply line, the boost power supply line and an output power supply line, and includes a plurality of switching elements. The second circuit outputs a voltage obtained by multiplying the voltage generated in the first circuit N times (M>N, M and N is a positive integer), between the first power supply line and the output power supply line by a charge-pump operation using a capacitor connected between first and second terminals outside and the switching element connected with the second terminal.

Abstract: A D/A conversion circuit includes a first D/A converter and a second D/A converter that respectively output a first voltage and a second voltage. An ith two-input selector among a plurality of input selectors of the first D/A converter selects a (4i+1)th input voltage or a (4i+3)th input voltage based on input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage. An ith three-input selector among a plurality of three-input selectors of the second D/A converter selects a 4ith input voltage, a (4i+2)th input voltage, or a (4i+4)th input voltage based on the input data, and outputs the selected input voltage to a selector of a selector block in the subsequent stage.

Abstract: A data driver includes a D/A conversion circuit, a switch circuit, and a data line driver circuit. The switch circuit includes a first switch element provided between a first voltage output node of the D/A conversion circuit and a first input node of a grayscale generation amplifier, a second switch element that is provided between a second voltage output node of the D/A conversion circuit and the first input node and is exclusively turned ON/OFF with respect to the first switch element, a third switch element provided between the first voltage output node and a second input node, and a fourth switch element that is provided between the second voltage output node and the second input node and is exclusively turned ON/OFF with respect to the third switch element.

Abstract: A data driver includes a D/A conversion circuit that receives grayscale data and outputs a first grayscale voltage and a second grayscale voltage corresponding to the grayscale data by time division in each of first to Nth sampling periods, and first to Nth data line driver circuits that share the D/A conversion circuit. Each of the first to Nth data line driver circuits includes a grayscale generation amplifier that samples the first grayscale voltage and the second grayscale voltage output from the D/A conversion circuit in a corresponding sampling period among the first to Nth sampling periods, and generates a grayscale voltage between the first grayscale voltage and the second grayscale voltage.

Abstract: A driver circuit for driving source lines of an electro-optical device includes first and second source short-circuit circuits that respectively short-circuit first and second source lines and a source short-circuit node, a source charge storage short-circuit circuit that short-circuits a source charge storage node connected with one end of a source capacitor and the source short-circuit node, a voltage setting circuit that supplies a given voltage to the source charge storage node, and a node short-circuit circuit that short-circuits a common electrode voltage output node and the source short-circuit node, a voltage output to a common electrode of the electro-optical device provided opposite to a pixel electrode through an electro-optical element being applied to the common electrode voltage output node.

Abstract: A display driver includes a common electrode charge storage switch provided between a first capacitor element connection node to which one end of a first capacitor element can be connected and a common electrode voltage output node to which a voltage of a common electrode opposite to a pixel electrode of an electro-optical device through an electro-optical material is supplied, a source charge storage switch provided between a second capacitor element connection node to which one end of a second capacitor element can be connected and a source voltage output node to which a voltage of a source line of the electro-optical device is supplied, and a node short circuit switch provided between the common electrode voltage output node and the source voltage output node.

Abstract: A comparator circuit includes a current mirror circuit, a differential pair, and a first current source between first and second power supply lines. The differential pair includes a first MOS transistor of enhancement mode n-type having a gate electrode at which an input signal is supplied, and a second MOS transistor of depletion mode n-type. A source of the second MOS transistor is connected with a source of the first MOS transistor and a threshold voltage of the second MOS transistor is lower than that of the first MOS transistor. A gate electrode of the first MOS transistor is formed by polycrystalline silicon which contains a p-type impurity. A gate electrode of the second MOS transistor is formed by polycrystalline silicon which contains an n-type impurity and is connected with the first power supply line. An output signal is output based on a drain voltage of the second MOS transistor.

Abstract: A boost clock generation circuit including: a first switch circuit connected between a first power supply line and a first clock output line to which the first boost clock signal is output; a second switch circuit connected between a second power supply line and the first clock output line; a third switch circuit connected between a third power supply line and a second clock output line to which the second boost clock signal is output; and a fourth switch circuit connected between a fourth power supply line and the second clock output line. One of the first and second switch circuits is exclusively turned ON, and one of the third and fourth switch circuits is exclusively turned ON. The level current drive capability of the first switch circuit differs from the level of current drive capability of the third switch circuit; and the level of current drive capability of the second switch circuit differs from the level of current drive capability of the fourth switch circuit.

Abstract: A booster circuit includes: first to M-th power supply lines (M is an integer greater than three); first to (M?2)th boost capacitors, the j-th boost capacitor (1?j?M?2, j is an integer) being connected between the j-th power supply line and the (j+1)th power supply line in a first period, and connected between the (j+1)th power supply line and the (j+2)th power supply line in a second period which is subsequent to the first period; and first to (M?3)th stabilization capacitors, the k-th stabilization capacitor (1?k?M?3, k is an integer) being connected between the (k+1)th power supply line and the (k+2)th power supply line, and storing an electric charge discharged from the k-th boost capacitor in the second period.

Abstract: A comparator circuit includes a current mirror circuit, a differential pair, and a first current source between first and second power supply lines. The differential pair includes a first MOS transistor of enhancement mode n-type having a gate electrode at which an input signal is supplied, and a second MOS transistor of depletion mode n-type. A source of the second MOS transistor is connected with a source of the first MOS transistor and a threshold voltage of the second MOS transistor is lower than that of the first MOS transistor. A gate electrode of the first MOS transistor is formed by polycrystalline silicon which contains a p-type impurity. A gate electrode of the second MOS transistor is formed by polycrystalline silicon which contains an n-type impurity and is connected with the first power supply line. An output signal is output based on a drain voltage of the second MOS transistor.