Abstract: A first circuit is connected with the first and second power supply lines and a boost power supply line, and outputs a voltage obtained by multiplying the voltage between the first and second power supply lines M times (M is a positive integer), between the first power supply line and the boost power supply line. A second circuit is connected with the first power supply line, the boost power supply line and an output power supply line, and includes a plurality of switching elements. The second circuit outputs a voltage obtained by multiplying the voltage generated in the first circuit N times (M>N, M and N is a positive integer), between the first power supply line and the output power supply line by a charge-pump operation using a capacitor connected between first and second terminals outside and the switching element connected with the second terminal.

Abstract: A booster circuit includes: first to M-th power supply lines (M is an integer greater than three); first to (M?2)th boost capacitors, the j-th boost capacitor (1?j?M?2, j is an integer) being connected between the j-th power supply line and the (j+1)th power supply line in a first period, and connected between the (j+1)th power supply line and the (j+2)th power supply line in a second period which is subsequent to the first period; and first to (M?3)th stabilization capacitors, the k-th stabilization capacitor (1?k?M?3, k is an integer) being connected between the (k+1)th power supply line and the (k+2)th power supply line, and storing an electric charge discharged from the k-th boost capacitor in the second period,

Abstract: A booster circuit including first to Mth power supply lines (M is an integer larger than 3) and first and second charge-pump circuits. Each of the charge-pump circuit has first to (M?2)th boost capacitors, wherein the jth boost capacitor (1?j?M?2, j is an integer) is connected between the jth power supply line and the (j+1)th power supply line in a first period and is connected between the (j+1)th power supply line and the (j+2)th power supply line in a second period subsequent to the first period. Each of the charge-pump circuits generates a boosted voltage by a charge-pump operation in different phases.

Abstract: A boost clock generation circuit including: a first switch circuit connected between a first power supply line and a first clock output line to which the first boost clock signal is output; a second switch circuit connected between a second power supply line and the first clock output line; a third switch circuit connected between a third power supply line and a second clock output line to which the second boost clock signal is output; and a fourth switch circuit connected between a fourth power supply line and the second clock output line. One of the first and second switch circuits is exclusively turned ON, and one of the third and fourth switch circuits is exclusively turned ON. The level of current drive capability of the first switch circuit differs from the level of current drive capability of the third switch circuit; and the level of current drive capability of the second switch circuit differs from the level of current drive capability of the fourth switch circuit.

Abstract: A semiconductor integrated circuit has a reset signal generation circuit (10) that generates a reset signal (12) having a reset period based on a power-on reset signal (11), and a latch circuit (20) having an initialization circuit (23) that initializes a latch output (21) based on the reset signal (12). The reset signal generation circuit (10) has a delay circuit (14) that can variably set a pulse width corresponding to the reset period of the reset signal (12). An output line of the delay circuit (14) is connected to a first pad terminal (32). An output line of the initialization circuit (23) is connected to a second pad terminal (34). When the semiconductor integrated circuit is verified, the first and second pad terminals (32, 34) are brought in contact with a probe (40).