Patents by Inventor Haruo Kojima
Haruo Kojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7009462Abstract: A limiter circuit comprises a quarter-wave transmission line, a first limiter element, a first DC return element, a second limiter element and a second DC return element. The quarter-wave transmission line, which has a predetermined characteristic impedance, comprises a signal line conductor and a common line conductor. The first limiter element is connected through a termination between the signal line conductor and the common line conductor at one side of the transmission line. The first DC return element is connected in parallel with the first limiter element. The second limiter element is connected between the signal line conductor and the common line conductor at another side of the transmission line. The second DC return element is connected to in parallel with the second limiter element.Type: GrantFiled: February 25, 2004Date of Patent: March 7, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Haruo Kojima
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Publication number: 20050275465Abstract: A first power source 11 for supplying a bias voltage to a gate electrode G of a field effect transistor 13, which amplifies high-frequency signals, and a second power source 15 for supplying a bias voltage to a drain electrode D of the field effect transistor 13 are provided. The protective resistance 12 is connected between the gate electrode G of the field effect transistor 13 and the first power source 11, and the bias voltage controller 14 is connected between the drain electrode D of the field effect transistor 13 and the second power source 11. Further, a voltage detector 16 is connected between both ends of the protective resistance 12 to detect a voltage drop generated between both ends of the protective resistance 12, when a rectified current flows to the gate electrode G from the drain electrode D of the field effect transistor 13.Type: ApplicationFiled: June 9, 2005Publication date: December 15, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Haruo Kojima
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Publication number: 20050104656Abstract: An amplifier includes a plurality of power amplifier elements connected in cascaded multiple stages, a first bias power supply, a second bias power supply, a switching circuit configured to switch a first output supplied from the first bias power supply in response to a modulation pulse so as to transmit the first output to the plurality of power amplifier elements, a pulse differentiating circuit configured to differentiate the modulation pulse by a given time constant, and an adder circuit configured to add the differentiated modulation pulse and a second output of the second bias power supply so as to transmit the differentiated modulation pulse added to the second output as an input bias voltage to at least one of the plurality of power amplifier elements except for a final stage in the cascaded multiple stages.Type: ApplicationFiled: August 31, 2004Publication date: May 19, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Haruo Kojima
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Publication number: 20050070051Abstract: In a method of manufacturing a semiconductor device of the invention, a rigid substrate which supports one or more semiconductor elements on a surface of the substrate and is clamped between an upper mold and a lower mold of an encapsulation mold at a time of resin encapsulation is provided, so that a vent-end edge portion of the substrate corresponding to a vent end of the encapsulation mold has a thickness smaller than a thickness of other portions of the substrate. The substrate is disposed in the encapsulation mold, and resin is injected into a cavity between the upper mold and the substrate to encapsulate the semiconductor elements with the resin.Type: ApplicationFiled: February 20, 2004Publication date: March 31, 2005Applicant: FUJITSU LIMITEDInventors: Youhei Nagahama, Katsunori Wako, Yuichi Asano, Masanori Takahashi, Haruo Kojima, Masamichi Fujimoto, Hiroshi Ohtsubo, Yuki Yasuda
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Publication number: 20050024159Abstract: A limiter circuit comprises a quarter-wave transmission line, a first limiter element, a first DC return element, a second limiter element and a second DC return element. The quarter-wave transmission line, which has a predetermined characteristic impedance, comprises a signal line conductor and a common line conductor. The first limiter element is connected through a termination between the signal line conductor and the common line conductor at one side of the transmission line. The first DC return element is connected in parallel with the first limiter element. The second limiter element is connected between the signal line conductor and the common line conductor at another side of the transmission line. The second DC return element is connected to in parallel with the second limiter element.Type: ApplicationFiled: February 25, 2004Publication date: February 3, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Haruo Kojima
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Patent number: 6762493Abstract: A microwave integrated circuit, includes: a dielectric substrate having a signal line on a front surface of the dielectric substrate and a mount pad disposed adjacent to an end of the signal line in a longitudinal direction of the signal line; a semiconductor chip having an upper electrode and a lower electrode provided on opposite surfaces of the semiconductor chip, the lower electrode being mounted on the mount pad; a bonding block connecting a bottom surface of the bonding block to the end in the longitudinal direction of the signal line; and a wiring member configured to bond the upper electrode of the semiconductor chip and a top surface of the bonding block together.Type: GrantFiled: March 12, 2003Date of Patent: July 13, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Haruo Kojima, Tomoyuki Kitani
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Publication number: 20030183927Abstract: A microwave integrated circuit, includes: a dielectric substrate having a signal line on a front surface of the dielectric substrate and a mount pad disposed adjacent to an end of the signal line in a longitudinal direction of the signal line; a semiconductor chip having an upper electrode and a lower electrode provided on opposite surfaces of the semiconductor chip, the lower electrode being mounted on the mount pad; a bonding block connecting a bottom surface of the bonding block to the end in the longitudinal direction of the signal line; and a wiring member configured to bond the upper electrode of the semiconductor chip and a top surface of the bonding block together.Type: ApplicationFiled: March 12, 2003Publication date: October 2, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Haruo Kojima, Tomoyuki Kitani
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Patent number: 6383397Abstract: A method for separating magnetic particles dispersed in a fluid by magnetic attraction, characterized in that an object fluid in which magnetic particles are dispersed is passed through a magnetized rotary tube, magnetic particles are made to adhere by magnetic attraction to magnetized surface in the tube, the flow of the fluid is suspended before the capacity of magnetic attraction of the tube lowers, the magnetized surface is demagnetized, an exhaust fluid for exhausting magnetic particles in the tube is made to flow under pressure through the tube, the exhaust fluid mixed with magnetic particles is discharged, and the magnetic particles are separated from the exhaust fluid.Type: GrantFiled: December 11, 2000Date of Patent: May 7, 2002Inventor: Haruo Kojima
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Patent number: 6166433Abstract: The semiconductor device includes a semiconductor chip, an FPC tape for mounting the semiconductor chip thereto, a mold resin for protecting the semiconductor chip, and metal balls provided on the FPC tape for connecting the semiconductor chip to a circuit board. The mold resin has the glass transition temperature not lower than 200.degree. C., the coefficient of linear expansion in the range from 13 to 18 ppm/.degree. C., and Young's modulus in the range from 1500 to 3000 kg/mm.sup.2, whereby warpage of the semiconductor device is mitigated. The semiconductor device can also include a buffer layer. The semiconductor device can be manufactured by collectively molding a plurality of semiconductor chips mounted to the FPC tape and by cutting the molded article into individual semiconductor packages.Type: GrantFiled: December 24, 1998Date of Patent: December 26, 2000Assignee: Fujitsu LimitedInventors: Akira Takashima, Hidehiko Akasaki, Haruo Kojima, Fumihiko Taniguchi, Kazunari Kosakai, Koji Honna, Toshihisa Higashiyama
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Patent number: 6138833Abstract: A placer gold separating method includes subjecting placer gold-and gold ore-containing sand and gravel layers accumulated on the bottom of the water of a river and placer gold- and gold ore-containing sand and gravel layers formed deep in the ground to excavation or suction excavation by utilizing a water pressure difference. This causes a mixture of the excavated or suction excavation placer gold- and gold ore-containing sand, gravel and water to flow horizontally by the action of a pressure fluid. The placer gold and gold ores are separated by utilizing a specific gravity difference while the mixture is flowing. A placer gold mining boat used to practice this method is provided thereon with a combination of a suction excavation component, a mixture transfer component, a component for separating placer gold by utilizing a specific gravity difference, and a component for discarding the remaining mixture from which the placer gold has been separated.Type: GrantFiled: April 26, 1999Date of Patent: October 31, 2000Assignee: Jipangu Inc.Inventors: Tamisuke Matsufuji, Haruo Kojima
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Patent number: 6023080Abstract: A semiconductor device comprises a dielectric substrate formed on a metal carrier, a semiconductor chip formed on the dielectric substrate and having a first electrode, a microstrip line formed on the dielectric substrate and having a second electrode to be connected to the first electrode, and wires, having different lengths, for connecting the first and second electrodes.Type: GrantFiled: February 11, 1998Date of Patent: February 8, 2000Assignee: Kabushiki Kaisha ToshibaInventor: Haruo Kojima
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Patent number: 5244512Abstract: A method for treating a metal surface with zinc phosphate of this invention can treat an iron-based surface, a zinc-based surface, an aluminum-based surface as well as a metal surface having two kinds or more of these surfaces with the same zinc phosphate treating solution, and even if treating times increases, the method makes it possible to form a coating film having superior adhesion and high corrosion resistance under a stable condition, and also, it prevents a precipitate formed by a metal ion eluted from a metal surface to be treated, especially, by an aluminum ion. A complex fluoride compound contained in said zinc phosphate treating solution of coming in contact with a metal surface is added so that a concentration (unit: g/l) converted into at least one of a hexafluorosilicic acid group (SiF.sub.6.sup.2-) and a tetrafluoroboric acid group (BF.sub.4.sup.-), with an aluminum ion concentration (unit: g/l) contained in said treating solution, is satisfactory for the following equation (I).Type: GrantFiled: May 15, 1992Date of Patent: September 14, 1993Assignee: Nippon Paint Co., Ltd.Inventors: Isao Kawasaki, Minoru Ishida, Asao Mochizuki, Haruo Kojima
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Patent number: 4710250Abstract: A package for a semiconductor device comprising three laminated ceramic sheets: a first sheet provided with a chip stage on the upper surface thereof, a second sheet provided with a first chip-inserting window for exposing the surface of the chip stage and provided with an internal conductor pattern formed at least on the upper surface thereof; and a third sheet provided with a second window for exposing the first chip-inserting window and for exposing a wire-bonding area located adjacent to the periphery of the first chip-inserting window, characterized in that marks for recognizing the location of the first chip-inserting window are essentially aligned, this alignment being effected in that the first chip-inserting window and marks for recognizing the location of the first chip-inserting window are simultaneously formed with the same mold, the marks for recognizing the location of the first chip-inserting window being formed in the wire-bonding area of the second green sheet.Type: GrantFiled: February 11, 1986Date of Patent: December 1, 1987Assignee: Fujitsu LimitedInventors: Haruo Kojima, Hidehiko Akasaki
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Patent number: 4278865Abstract: A stud welding method uses an inert mixed gas as arc shield in performing stud welding on a base metal, such as, vehicle body, by utilizing the stud, e.g. a T-stud, as an electrode, the stud serving as the positive pole while the base metal serves as the negative pole to thereby prevent formation of oxide film on the base metal surface during the welding, the inert mixed gas comprising carbon dioxide gas and argon gas.Type: GrantFiled: April 16, 1979Date of Patent: July 14, 1981Assignee: Nippon Stud Welding Co. Ltd.Inventors: Hiroyuki Watanabe, Eiji Miyoshi, Haruo Kojima, Takeshi Yoshida, Masaaki Kato, Shizuo Miyazaki