Abstract: An information recording system includes a recording medium capable of limiting a function by password and an information recording device for controlling the recording medium. The recording medium stores an input password, counts updating event(s) of a password, stores the update count of the password, outputs information stored in the password related information storage according to a READ request issued from the information recording device, compares a input password with a password stored in the password register, limits a predetermined function of the recording medium according to the comparison result from the password comparator. The information recording device stores a password and a password identification ID which is associated with the update count of the password, selects a password with reference to the update count of the password and the password identification ID and outputs the selected password into the recording medium to compare the passwords.

Abstract: An information recording system includes a recording medium capable of limiting a function by password and an information recording device for controlling the recording medium. The recording medium stores an input password, counts updating event (s) of a password, stores the update count of the password, outputs information stored in the password related information storage according to a READ request issued from the information recording device, compares a input password with a password stored in the password register, limits a predetermined function of the recording medium according to the comparison result from the password comparator. The information recording device stores a password and a password identification ID which is associated with the update count of the password, selects a password with reference to the update count of the password and the password identification ID and outputs the selected password into the recording medium to compare the passwords.

Abstract: A semiconductor memory device according to the present invention comprises a housing including a card bus connector for connection to a host device and having a PC card shape having a thickness of 5.0 mm, four SD memory cards housed in the housing and a control circuit for controlling transmission/reception of a signal between the card bus connector and the respective SD memory cards. The semiconductor memory device is suitably used as a recording medium of a host device for which a higher data transfer rate and a larger memory capacity are demanded. Further, a semiconductor memory device, which is attachable and detachable relative to the host device and thereby portable, and relatively inexpensively obtainable, can be provided, and is directly insertable into a laptop personal computer to be used.

Abstract: In a recording device having one or more semiconductor memories mounted thereon, the number of semiconductor memories operating in parallel is restricted according to an available supply current of an accessing apparatus to which the recording device is attached.

Abstract: A memory card is equipped in a host apparatus and used for data recording. The memory card has a built-in flash memory and an internal ROM, and there is prestored a predetermined writable block size corresponding to a certain integral multiple of a size of an erase block. A write block size of a write command is issued by the host apparatus. The data size is detected and compared to the writable block size, so as to decide whether the write block size is an integral multiple of the writable block size, thereby judging whether write is permitted. Only when the write is permitted, data is written from the host apparatus into the memory card. If the write is not permitted, a response to inform an error is returned to the host apparatus.

Abstract: A memory card is equipped in a host apparatus and used for data recording. The memory card has a built-in flash memory and an internal ROM, there is prestored a predetermined writable block size corresponding to a certain integral multiple of a size of an erase block. A write block size of a write command issued by the host apparatus. The data size is detected and compared to the writable block size, so as to decide whether the write block size is an integral multiple of the writable block size, thereby judging whether write is permitted. Only when the write is permitted, data is written from the host apparatus into the memory card. If the write is not permitted, a response to inform an error is returned to the host apparatus.

Abstract: [Problem] As to a memory card drive for operating multiple memory cards in parallel and executing high speed reading and writing, the amount of current supplied to the memory card drive varies among apparatuses connected and supplying electric power to the memory card drive due to their different capabilities, and therefore apparatuses applicable to the memory card drive are limitd. [Means for Solving the Problem] In a recording device having one or more semiconductor memories mounted thereon, the number of semiconductor memories operating in parallel is restricted according to the available supply current of an accessing apparatus to which the recording device is attached.

Abstract: A semiconductor memory device according to the present invention comprises a hosing including a card bus connector for connection to a host device and having a PC card shape having the thickness of 5.0 mm, four SD memory cards (R: Registered trade mark) housed in the housing and a control circuit for controlling transmission/reception of a signal between the card bus connector and the respective SD memory cards (R: Registered trade mark). The semiconductor memory device is suitably used as a recording medium of the host device for which a higher data transfer rate and a larger memory capacity are demanded. Further, a semiconductor memory device, which is attachable and detachable relative to the host device and thereby portable, and relatively inexpensively obtainable, can be provided, and is directly insertable into a laptop personal computer to be used.

Abstract: A reproduction signal 10 is processed in an AD converter 4 and an equalizer 16 to be a decoder input signal 12. The decoder input signal 12 is used to calculate a phase error signal 25 and a quality judgement signal 26. A phase-frequency error detection circuit 22 retains a sign of the phase error signal 25 obtained when the quality judgement signal 26 is changed in quality from “good” to “bad”. The phase-frequency error detection circuit 22 then outputs, as a phase-frequency error signal 27, the phase error signal 25 when the signal quality is “good”, and a given value corresponding to the retained sign when the signal quality is “bad”. A voltage controlled oscillator 9 generates a recovered clock signal 11 whose frequency is based on the oscillation control signal 15 generated by the phase-frequency error signal 27.

Abstract: A data detecting method and its apparatus for equalizing an input signal reproduced from magnetic recording media by partial response by employing at least one of partial response class 4 (PR4) and extended partial response class 4 (EPR4), and decoding the input signal. The input signal is equalized by PR4, and a first equalized signal is obtained. First decoded data is obtained from the first equalized signal. The input signal is equalized by EPR4, and a second equalized signal is obtained. Second decoded data is obtained from the second equalized signal. From the first equalized signal and second equalized signal, the signal condition of the input signal is judged, and the optimum data detecting method is discriminated. Thus, either the first decoded data or second decoded data is selected as detected data.

Abstract: In order to construct a PLL circuit corresponding to the plurality of reproduction channel rates by using only a digital loop filter, the generation of a clock in accordance with the reproduction signal, of which the reproduction channel rate varies, is implemented with only one voltage control oscillator 7 in the case when the channel rate of the reproduction signal reproduced from the reproducer 1 varies at n/m of the basic channel rate at the time of recording by allowing the divider 6 to convert the output of the voltage control oscillator 7, which oscillates at the basic channel rate, into a reproduction clock through the n/m division.

Abstract: A reproduced signal is adaptively equalized in an adaptive equalizer after going through an AD converter. The AD converter, the adaptive equalizer, a phase error detector, a phase shifter, a DA converter, a loop filter, and a variable frequency oscillation circuit, all of which structure a PLL circuit, and a clock signal phase-locked to reproduced data is fed back to the AD converter. The phase shifter slightly shifts, as appropriate, a phase error detected in the phase detector according to the change in a barycenter of tap coefficients detected in a tap barycenter detection circuit. With such structure, signals can be processed in an accurate manner without causing competition in operation between the PLL and adaptive equalization.

Abstract: A reproduction signal 10 is processed in an AD converter 4 and an equalizer 16 to be a decoder input signal 12. The decoder input signal 12 is used to calculate a phase error signal 25 and a quality judgement signal 26. A phase-frequency error detection circuit 22 retains a sign of the phase error signal 25 obtained when the quality judgement signal 26 is changed in quality from “good” to “bad”. The phase-frequency error detection circuit 22 then outputs, as a phase-frequency error signal 27, the phase error signal 25 when the signal quality is “good”, and a given value corresponding to the retained sign when the signal quality is “bad”. A voltage controlled oscillator 9 generates a recovered clock signal 11 whose frequency is based on the oscillation control signal 15 generated by the phase-frequency error signal 27.

Abstract: A reproduction signal 10 is processed in an AD converter 4 and an equalizer 16 to be a decoder input signal 12. The decoder input signal 12 is used to calculate a phase error signal 25 and a quality judgement signal 26. A phase-frequency error detection circuit 22 retains a sign of the phase error signal 25 obtained when the quality judgement signal 26 is changed in quality from “good” to “bad”. The phase-frequency error detection circuit 22 then outputs, as a phase-frequency error signal 27, the phase error signal 25 when the signal quality is “good”, and a given value corresponding to the retained sign when the signal quality is “bad”. A voltage controlled oscillator 9 generates a recovered clock signal 11 whose frequency is based on the oscillation control signal 15 generated by the phase-frequency error signal 27.

Abstract: A data detecting method and its apparatus for equalizing an input signal reproduced from magnetic recording media by partial response by employing at least one of partial response class 4 (PR4) and extended partial response class 4 (EPR4), and decoding the input signal. The input signal is equalized by PR4, and a first equalized signal is obtained. First decoded data is obtained from the first equalized signal. The input signal is equalized by EPR4, and a second equalized signal is obtained. Second decoded data is obtained from the second equalized signal. From the first equalized signal and second equalized signal, the signal condition of the input signal is judged, and the optimum data detecting method is discriminated. Thus, either the first decoded data or second decoded data is selected as detected data.

Abstract: In a recording and reproducing apparatus having a simultaneous reproducing function, an adaptive filter outputs a pseudo crosstalk signal which approximates to frequency characteristics of crosstalk components leaking from recording data into a reproduced signal, and a subtractor subtracts the pseudo crosstalk signal from the reproduced signal, thereby canceling the crosstalk components

Abstract: A magnetic recording/reproducing apparatus is provided in which among diametrically oppositely disposed heads, a recording head and an erasing head of a same channel are disposed adjacently to each other. The recording head is disposed so as to precede by two tracks the erasing head with respect to a direction of cylinder rotation, when insert-editing, using a reproduced signal obtained by the recording head, erase and record timing setting and head tracking are performed and an erasing current is not applied during the reproduction by the recording head. The reproducing heads are disposed so as to be angularly apart by about 90 degrees from the recording and erasing heads, and a rotary transformer for reproduction is applied with a shield measure and then, formed as a core independently at an upper portion of the cylinder. In addition, more narrow tracks are compatibly reproduced by the recording head.

Abstract: A magnetic a tape recording/reproducing apparatus comprises a tape running unit, a recording and reproducing unit, a data memory, and a controller. The controller controls the tape running unit, the data memory and the recording and reproducing unit such that, in a recording mode, the input data are continuously written into the data memory at a first a data rate and the written data are intermittently read out from the data memory at a second data rate which is higher than the first data rate and intermittently recorded onto a magnetic tape, and that, in a reproduction mode, the recorded data are intermittently reproduced from the magnetic tape and intermittently written into the data memory at the second data rate and the written data are continuously read out from the data memory at the first data rate.

Abstract: A digital modulating/demodulating apparatus includes a demodulator for demodulating a modulated signal into a demodulated positional signal in response to a receipt of the modulated signal, a decoder for decoding the demodulated positional signal into a digital signal of N bits. A previous signal point on the constellation plane is defined by a previous demodulated positional signal and a current signal point on the constellation plane is defined by a current demodulated positional signal. The decoder outputs a digital signal of N bits, based on en amplitude and a phase of the previous signal point and the amplitude and the phase of the current signal point.

Abstract: A magnetic recording/reproducing apparatus is provided in which among diametrically oppositely disposed heads, a recording head and an erasing head of a same channel are disposed adjacently to each other. The recording head is disposed so as to precede by two tracks the erasing head with respect to a direction of cylinder rotation, when insert-editing, using a reproduced signal obtained by the recording head, erase and record timing setting and head tracking are performed and an erasing current is not applied during the reproduction by the recording head. The reproducing heads are disposed so as to be angularly apart by about 90 degrees from the recording and erasing heads, and a rotary transformer for reproduction is applied with a shield measure and then, formed as a core independently at an upper portion of the cylinder. In addition, more narrow tracks are compatibly reproduced by the recording head.