Abstract: A vehicle control device is configured to control a vehicle equipped with (i) an optical sensor configured to acquire a reflected light image by sensing reflected light of irradiated light and (ii) a sensing camera configured to acquire a camera image according to intensity of outside light in a sensing area which overlaps with a sensing area of the optical sensor. The vehicle control device includes an extraction unit configured to extract an unmatched pixel group by comparing the reflected light image with the camera image, and a control unit configured to instruct the vehicle to control according to a water-related substance estimated to correspond to the unmatched pixel group.

Abstract: A cleaning control device is configured to control a cleaning system of a vehicle equipped with (i) an optical sensor configured to acquire an outside light image according to intensity of outside light while light irradiation for sensing reflected light is stopped, (ii) a sensing camera configured to acquire a camera image according to the intensity of the outside light, and (iii) the cleaning system configured to clean an incident surface on which light is incident from sensing areas of the optical sensor and the sensing camera overlapping with each other. The cleaning control device includes an extraction unit configured to extract an unmatched pixel group by comparing the outside light image with the camera image, and a control unit configured to instruct the cleaning system to perform cleaning control to remove dirt from the incident surface, the dirt being estimated to correspond to the unmatched pixel group.

Abstract: A measurement apparatus unit is mounted to a vehicle. The measurement apparatus unit includes a base and a plurality of detection modules. The plurality of detection modules are mounted to the base. Each of the plurality of detection modules includes a casing and a detector. The detector is housed in the casing. The casing includes a mounting portion for detachably mounting each of the plurality of detection modules to the base. The mounting portion has a shape that is common among the plurality of detection modules.

Abstract: An object detection device includes a light emitting section that radiates detection light, a light receiving section that includes a plurality of pixels and outputs pixel values of the respective pixels corresponding to intensity of incident light, an irradiation control section that causes the light emitting section to radiate the detection light with predetermined reference intensity or at least one discrimination intensity different from the reference intensity, a specification section that specifies the pixels whose pixel value, which is output from the light receiving section depending on irradiation with the reference intensity and irradiation with the discrimination intensity, has changed, and an identification section that identifies an object by using the pixel value, which concerns the specified pixel, included in the pixel values output from the receiving section depending on the irradiation with the reference intensity.

Abstract: A measurement apparatus unit is mounted to a vehicle. The measurement apparatus unit includes a base and a plurality of detection modules. The plurality of detection modules are mounted to the base. Each of the plurality of detection modules includes a casing and a detector. The detector is housed in the casing. The casing includes a mounting portion for detachably mounting each of the plurality of detection modules to the base. The mounting portion has a shape that is common among the plurality of detection modules.

Abstract: In a pulse wave analyzer, an ECG signal and a pulse wave signal are detected from an object to be analyzed. A plurality of feature points are extracting from the acquired ECG signal, the feature points appearing in a waveform of the ECG signal. The acquired pulse wave signal is segmented into a plurality of pulse wave signal pieces based on times at which the feature points appear. Each of the pulse wave signal pieces is segmented every heart beat. A reference pulse wave is calculated based on the plurality of pulse wave signal pieces, by multiplying the pulse wave signal pieces by coefficients and averaging the pulse wave signal pieces multiplied by the coefficients. The reference pulse wave is used to estimate the blood pressure of the object.

Abstract: An electrocardiograph includes first and second induction electrodes, a signal difference generation section, an electrocardiographic detection section, a signal applying section, and a contact detection section. The signal difference generation section generates a potential difference between a signal from the first induction electrode and a signal from the second induction electrode as a signal difference. The electrocardiographic detection section detects an electrocardiographic complex of a subject based on the signal difference. The signal applying section applies a first signal to the first induction electrode and a second signal to the second induction electrode. The first signal has a property different from the electrocardiographic complex. The second signal has a property different from the electrocardiographic complex and the first signal. The contact detection section detects a contact state of the subject to the first and second induction electrodes based on the signal difference.

Abstract: An electrocardiograph includes first and second induction electrodes, a signal difference generation section, an electrocardiographic detection section, a signal applying section, and a contact detection section. The signal difference generation section generates a potential difference between a signal from the first induction electrode and a signal from the second induction electrode as a signal difference. The electrocardiographic detection section detects an electrocardiographic complex of a subject based on the signal difference. The signal applying section applies a first signal to the first induction electrode and a second signal to the second induction electrode. The first signal has a property different from the electrocardiographic complex. The second signal has a property different from the electrocardiographic complex and the first signal. The contact detection section detects a contact state of the subject to the first and second induction electrodes based on the signal difference.

Abstract: In a pulse wave analyzer, an ECG signal and a pulse wave signal are detected from an object to be analyzed. A plurality of feature points are extracting from the acquired ECG signal, the feature points appearing in a waveform of the ECG signal. The acquired pulse wave signal is segmented into a plurality of pulse wave signal pieces based on times at which the feature points appear. Each of the pulse wave signal pieces is segmented every heart beat. A reference pulse wave is calculated based on the plurality of pulse wave signal pieces, by multiplying the pulse wave signal pieces by coefficients and averaging the pulse wave signal pieces multiplied by the coefficients. The reference pulse wave is used to estimate the blood pressure of the object.

Abstract: A decoder decodes a branch instruction. An operating section executes logical, arithmetic, and shift operations. A register file store operation result of the operating section. A program counter counting the address of the present programs. A direct-setting bus is provided to allowing the decoder to directly set an immediate value to the program counter without passing through an output bus of the operating section. And, a switch selectively connects the direct-setting bus or the output bus to the program counter.

Abstract: A multiplying device operates for implementing multiplication between multiplicand data and multiplier data in a two's complement representation form. Each of the multiplicand data and the multiplier data has n bits, where n denotes a predetermined even number. A 1-bit sign extension of the multiplicand data is executed to generate data having n+1 bits. In the multiplying device, n/2 partial product data pieces are generated on the basis of the data having n+1 bits and the multiplier data according to second-order Booth's algorithm. Each of the n/2 partial product data pieces has n+1 bits. There is a plurality of adders connected and arranged in a tree configuration. The adders operate for adding the n/2 partial product data pieces. The adders include a final-stage adder which outputs multiplication result data representing a product of the multiplicand data and the multiplier data. The multiplication result data has 2n−1 bits.

Abstract: An information processing apparatus such as a microcomputer consisting of a CPU and a coprocessor is provided. The CPU and the coprocessor are connected through a data bus and an address bus. Switches are disposed in the data bus and the address bus which block communication between the CPU and the coprocessor upon execution of an instruction in the coprocessor, thereby allowing the CPU 1 to operate in parallel to the coprocessor.

Abstract: A pipeline processing apparatus for performing processing operations in a succession of processing cycles, in which each cycle is composed of a succession of stages that include an instruction decoding stage for decoding an instruction associated with the cycle and an execution stage for executing an operation dependent on the instruction, and the processing cycles include a first cycle which starts at a first time and a second cycle that begins at a second time that is after the first time and that overlaps the first cycle in time. The apparatus is constructed and controlled for causing a branch instruction to be decoded in the instruction decoding stage of the first cycle; and for effecting a calculation in the execution stage of the first cycle, dependent on the branch instruction decoded in the instruction decoding stage of the first cycle.

Abstract: An information processing apparatus and method, such that when an interruption occurs in a microprocessor, an exception processing sequence control is started, a program condition of an interrupted program and an address of the interrupted program are saved in a RAM, a program address of a jump instruction is read out from an exception processing generating source and is set in a program counter, and the exception processing sequence control is stopped. Thereafter, a normal processing sequence control is started, the jump instruction is read out from a ROM, an address of an exception processing vector is calculated according to the jump instruction, the exception processing vector is read out from the ROM, a branch address of an exception processing routine indicated by the exception processing vector is set in the program counter, and an operation state of the microprocessor is branched to the exception processing routine.

Abstract: A semiconductor device, which can realize a high speed operation of a transistor with a small leakage current whenever such operation is required, is disclosed. A SOI layer is formed on a monocrystalline silicon substrate through a silicon oxide film, and C-MOS circuits (inverter circuits) are configured with P-channel type MOSFETs and N-channel type MOSFETs on the layer. A bias electrode for P-channel is disposed within the silicon oxide film facing the P-channel type MOSFETs, while a bias electrode for N-channel is disposed within the silicon oxide film facing the N-channel type MOSFETs.

Abstract: An 8-bit CLA adder is constructed for inputting 4 lower bits a3:0,b3:0 and 4 upper bits a7:4,b7:4 of two input signals to the two 4-bit full adders 2,12 and a carry c-1 to the lowest bit the full adder of the first-stage 2 to generate carries c3,c7 correspondint to the third and seventh bit of the input signals from a carry generation signal g7:0 and a carry propagation signal p7:0 generated by the both adders 2,12 and the carry c-1. The full adder of the second-stage 12 is constructed to add the 4 upper bits a7:4,b7:4 with setting a carry-in as 0 so as to generate a temporary summing signal sz7:4. A logical circuit 14 generates a true sum of 4 upper bits from a carry c3 to the third bit to the forth bit, a temporary sum sz7:4 and a carry propagation signal p7:4 generated by the full adder of the second-stage 12.

Abstract: A SOI semiconductor integrate circuit device, which can protect against surges between a signal-input terminal and power-supply input terminal thereof to obtain an improved electrostatic withstand quantity, is disclosed. An inverter circuit which is an integrated circuit is formed in a thin-film semiconductor layer formed through an insulation film on a p-type silicon substrate. An n-type diode diffusion region, resistor diffusion region, and FET diffusion region are formed within the silicon substrate. An input portion of the inverter circuit is connected through the resistor diffusion region to a signal-input terminal IN. A power-supply input terminal VC is connected to a ground terminal GND through a reverse-biased diode D formed by the diode diffusion region. When surge is applied to the signal-input terminal IN, a parasitic diode DD composed by the resistor diffusion region and silicon substrate exhibits avalanche breakdown and surge voltage is bypassed.

Abstract: A pipeline arithmetic and logic system capable of adjusting operational timings among stages without using an NOP instruction, providing a size reduction of its control section. The system has a decoder set including decoder groups divided into a decoder group for controlling an arithmetic section unit, a register file unit and a program counter unit, and a decoder for control of an address unit, and further including a clock control unit controlled by the address unit control decoder. A clock signal from an external source is directly fed to the address unit while being fed through the clock control unit to the other units. When fetching a data transfer instruction and repeatedly executing an MA stage twice, the system stops the clock control unit at the execution of the first MA stage to inhibit the operations of the units other than the address unit.

Abstract: With N-bit mask bit data, a bit mask generator generates (L.times.M.times.N)-bit mask data in which the N-bit mask bit data is disposed in one of L.times.M consistent blocks which is specified by M-bit block selection data and L-bit super-block selection data and each bit of the other blocks are stuffed with a stuffing bit. The bit mask generator comprises a first mask generator responsive to the block selection data for generating first mask data by disposing the N-bit mask bit data in one of M blocks of N bits which is specified by one of the M-bit block selection data, and a second mask generator responsive to the super-block selection data for generating the final mask data by disposing the first mask data in one of L super-blocks of M blocks which is specified by one of the L-bit super-block selection data. A bit field operation is performed by using the generated mask data.

Abstract: A multi-channel type intelligent power IC which solves the problems of parasitic transistor and increase in an area of isolation region, both of which are inherent problem in a pn junction isolation substrate. The power IC also enhances heat-radiation performance. An n type first semiconductor substrate and p type second semiconductor substrate are directly bonded, and a buried oxide film is formed in a portion of a bonding interface thereof. Subsequently, a plurality of isolation trenches are formed and the first semiconductor substrate is separated into an SOI isolation region and a pn isolation region. Logic elements are then formed in the SOI isolation region, and power elements are formed in the pn isolation region. In the case wherein two or more logic elements are hereby formed, the logic elements are isolated by isolation trenches. In the case wherein two or more power elements are formed, a parasitic current extracting portion is formed between mutual power elements.