Abstract: A converter is provided having a layout which can be easily designed and which requires a small chip area. Four MOS transistors having the same layout are disposed on the same substrate, and a polycrystalline silicon layer extends under the MOS transistors in the substrate. A predetermined voltage is applied to the polycrystalline silicon layer. This applied voltage continuously controls threshold voltages of the MOS transistors. An analog signal is input to gate terminals of the MOS transistors and is digitized in accordance with on and off states of the MOS transistors.

Abstract: A pn diode as an electrostatic discharge protection element of a MOSFET in a semiconductor device having an SOI structure to enable large current to flow is disclosed. N.sup.+ layers and p.sup.+ layers are formed on a surface of an element-isolation region isolated from another element region by dielectrics, and a polycrystalline silicon layer is formed by burying under these. Accordingly, the n.sup.+ layer and p.sup.+ layer and the n.sup.+ layer and p.sup.+ layer are respectively connected electrically via the polycrystalline silicon layer, structuring pn diodes. Consequently, the respective pn diodes become vertical pn junctions and it becomes possible to allow large current flow. Additionally, a MOSFET is formed on the dielectric in another element region, and a pn diode functions as an electrostatic discharge protection element of this MOSFET.

Abstract: A multi-channel type intelligent power IC which solves the problems of parasitic transistor and increase in an area of isolation region, both of which are inherent problem in a pn junction isolation substrate. The power IC also enhances heat-radiation performance. An n type first semiconductor substrate and p type second semiconductor substrate are directly bonded, and a buried oxide film is formed in a portion of a bonding interface thereof. Subsequently, a plurality of isolation trenches are formed and the first semiconductor substrate is separated into an SOI isolation region and a pn isolation region. Logic elements are then formed in the SOI isolation region, and power elements are formed in the pn isolation region. In the case wherein two or more logic elements are hereby formed, the logic elements are isolated by isolation trenches. In the case wherein two or more power elements are formed, a parasitic current extracting portion is formed between mutual power elements.