Abstract: On-chip jitter testing includes providing a clock signal to a circuit under test and delaying outputs from the circuit under test by predetermined delay values. For each delay value, a corresponding output from the circuit under test is compared with a reference signal derived from the clock signal to produce a bit error rate count for each delay value. A jitter value in the output of the circuit under test is determined based on the bit error rate counts.

Abstract: An analog filter in an integrated circuit is tested by placing the filter in a feedback loop. The filter is tested by determining whether the analog filter, while in the feedback loop, provides a signal that oscillates within a predetermined tolerance of an expected frequency.

Abstract: A method and circuitry for implementing a built-in self test (BIST) for determining the frequency characteristics of filter circuits in mixed-signal integrated circuits (ICs). The method comprises inserting a Circuit Under Test (CUT) into a feedback loop that looks like a sigma delta modulation loop and adjust the feedback loop so that it oscillates at the cut-off frequency of the filter. The frequency of oscillation can then easily be measured using either on on-chip counter or digital automated testing equipment. The feedback loop preferably comprises a comparator, a phase-delay component, such as a delay-line, and a one-bit DAC (digital-to-analog converter), wherein the comparator is connected to the output of the CUT, and the output of the one-bit DAC is connected to the input of the CUT. The phase delay of the feedback loop can be tuned through adjustment of the delay-line (e.g., an n-length shift register) until an oscillation frequency is obtained.